diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-06 23:28:24 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-06 23:28:24 +0000 |
| commit | 77e1ebd18fc558620b97fe38f3ebbf825533655f (patch) | |
| tree | 1797bafe61c35798adc83062bd4aa059e1ea52cb /test | |
| parent | 0b3d39235aaed8bc66ccffb3942bf7b5f185329c (diff) | |
| download | llvm-77e1ebd18fc558620b97fe38f3ebbf825533655f.tar.gz llvm-77e1ebd18fc558620b97fe38f3ebbf825533655f.tar.bz2 llvm-77e1ebd18fc558620b97fe38f3ebbf825533655f.tar.xz | |
[mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/o32_cc_byval.ll | 33 | ||||
| -rw-r--r-- | test/MC/Mips/xgot.ll | 4 |
2 files changed, 19 insertions, 18 deletions
diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index e17830d33a..5db47acc5a 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -10,22 +10,23 @@ define void @f1() nounwind { entry: -; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1) -; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) -; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) -; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) -; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) -; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) -; CHECK: sw $[[R6]], 36($sp) -; CHECK: sw $[[R5]], 32($sp) -; CHECK: sw $[[R4]], 28($sp) -; CHECK: sw $[[R3]], 24($sp) -; CHECK: sw $[[R7]], 20($sp) -; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) -; CHECK: sw $[[R2]], 16($sp) -; CHECK: lw $6, %lo(f1.s1)($[[R1]]) -; CHECK: lw $7, 4($[[R0]]) +; CHECK-LABEL: f1: +; CHECK-DAG: lw $[[R1:[0-9]+]], %got(f1.s1) +; CHECK-DAG: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) +; CHECK-DAG: lw $[[R7:[0-9]+]], 12($[[R0]]) +; CHECK-DAG: lw $[[R3:[0-9]+]], 16($[[R0]]) +; CHECK-DAG: lw $[[R4:[0-9]+]], 20($[[R0]]) +; CHECK-DAG: lw $[[R5:[0-9]+]], 24($[[R0]]) +; CHECK-DAG: lw $[[R6:[0-9]+]], 28($[[R0]]) +; CHECK-DAG: sw $[[R6]], 36($sp) +; CHECK-DAG: sw $[[R5]], 32($sp) +; CHECK-DAG: sw $[[R4]], 28($sp) +; CHECK-DAG: sw $[[R3]], 24($sp) +; CHECK-DAG: sw $[[R7]], 20($sp) +; CHECK-DAG: lw $[[R2:[0-9]+]], 8($[[R0]]) +; CHECK-DAG: sw $[[R2]], 16($sp) +; CHECK-DAG: lw $6, %lo(f1.s1)($[[R1]]) +; CHECK-DAG: lw $7, 4($[[R0]]) %agg.tmp10 = alloca %struct.S3, align 4 call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind call void @callee2(%struct.S2* byval @f1.s2) nounwind diff --git a/test/MC/Mips/xgot.ll b/test/MC/Mips/xgot.ll index e2a500ffde..cc336788aa 100644 --- a/test/MC/Mips/xgot.ll +++ b/test/MC/Mips/xgot.ll @@ -14,10 +14,10 @@ entry: ; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16 ; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_HI16 ; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_LO16 -; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT -; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16 ; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_HI16 ; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_LO16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16 ; CHECK: ] %0 = load i32* @ext_1, align 4 |