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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-08 18:05:02 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-08 18:05:02 +0000 |
| commit | 7db2d3a504713fce68bb859996994126af823ed0 (patch) | |
| tree | 50e48d593bffdfe02e3e79c876166e3d5e9acbe9 /test | |
| parent | 5d97ee31bb6ba2b72e2bef862ec7c07729447cc0 (diff) | |
| download | llvm-7db2d3a504713fce68bb859996994126af823ed0.tar.gz llvm-7db2d3a504713fce68bb859996994126af823ed0.tar.bz2 llvm-7db2d3a504713fce68bb859996994126af823ed0.tar.xz | |
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/avx-load-store.ll | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll index f70291b96e..1fda9bc229 100644 --- a/test/CodeGen/X86/avx-load-store.ll +++ b/test/CodeGen/X86/avx-load-store.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; RUN: llc -O0 < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s -check-prefix=CHECK_O0 ; CHECK: vmovaps ; CHECK: vmovaps @@ -78,3 +79,27 @@ entry: ret void } +declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind + +; CHECK_O0: _f_f +; CHECK-O0: vmovss LCPI +; CHECK-O0: vxorps %xmm +; CHECK-O0: vmovss %xmm +define void @f_f() nounwind { +allocas: + br i1 undef, label %cif_mask_all, label %cif_mask_mixed + +cif_mask_all: ; preds = %allocas + unreachable + +cif_mask_mixed: ; preds = %allocas + br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check + +cif_mixed_test_all: ; preds = %cif_mask_mixed + call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <8 x float> undef) nounwind + unreachable + +cif_mixed_test_any_check: ; preds = %cif_mask_mixed + unreachable +} + |