Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 168 insertions, 0 deletions

diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt
index c04dcd099b..54b242d7b2 100644
--- a/test/MC/Disassembler/X86/intel-syntax.txt
+++ b/test/MC/Disassembler/X86/intel-syntax.txt
@@ -20,3 +20,60 @@
 
 # CHECK: in AL, DX
 0xec
+
+# CHECK: nop
+0x90
+
+# CHECK: xchg EAX, R8D
+0x41 0x90
+
+# CHECK: xchg RAX, R8
+0x49 0x90
+
+# CHECK: add AL, 0
+0x04 0x00
+
+# CHECK: add AX, 0
+0x66 0x05 0x00 0x00
+
+# CHECK: add EAX, 0
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: add RAX, 0
+0x48 0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adc AL, 0
+0x14 0x00
+
+# CHECK: adc AX, 0
+0x66 0x15 0x00 0x00
+
+# CHECK: adc EAX, 0
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: adc RAX, 0
+0x48 0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmp AL, 0
+0x3c 0x00
+
+# CHECK: cmp AX, 0
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmp EAX, 0
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: cmp RAX, 0
+0x48 0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: test AL, 0
+0xa8 0x00
+
+# CHECK: test AX, 0
+0x66 0xa9 0x00 0x00
+
+# CHECK: test EAX, 0
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: test RAX, 0
+0x48 0xa9 0x00 0x00 0x00 0x00
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index fc64d64687..cfaeb06d72 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -309,5 +309,59 @@
 # CHECK: invvpid (%rax), %rax
 0x66 0x0f 0x38 0x81 0x00
 
+# CHECK: nop
+0x90
+
 # CHECK: xchgl %r8d, %eax
 0x41 0x90
+
+# CHECK: xchgq %r8, %rax
+0x49 0x90
+
+# CHECK: addb $0, %al
+0x04 0x00
+
+# CHECK: addw $0, %ax
+0x66 0x05 0x00 0x00
+
+# CHECK: addl $0, %eax
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: addq $0, %rax
+0x48 0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adcb $0, %al
+0x14 0x00
+
+# CHECK: adcw $0, %ax
+0x66 0x15 0x00 0x00
+
+# CHECK: adcl $0, %eax
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: adcq $0, %rax
+0x48 0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmpb $0, %al
+0x3c 0x00
+
+# CHECK: cmpw $0, %ax
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmpl $0, %eax
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: cmpq $0, %rax
+0x48 0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: testb $0, %al
+0xa8 0x00
+
+# CHECK: testw $0, %ax
+0x66 0xa9 0x00 0x00
+
+# CHECK: testl $0, %eax
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: testq $0, %rax
+0x48 0xa9 0x00 0x00 0x00 0x00
diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index 75e6b16986..c0164cbbcf 100644
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -327,3 +327,60 @@
 
 # CHECK: invvpid (%eax), %eax
 0x66 0x0f 0x38 0x81 0x00
+
+# CHECK: nop
+0x90
+
+# CHECK: addb $0, %al
+0x04 0x00
+
+# CHECK: addw $0, %ax
+0x66 0x05 0x00 0x00
+
+# CHECK: addl $0, %eax
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adcb $0, %al
+0x14 0x00
+
+# CHECK: adcw $0, %ax
+0x66 0x15 0x00 0x00
+
+# CHECK: adcl $0, %eax
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmpb $0, %al
+0x3c 0x00
+
+# CHECK: cmpw $0, %ax
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmpl $0, %eax
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: testb $0, %al
+0xa8 0x00
+
+# CHECK: testw $0, %ax
+0x66 0xa9 0x00 0x00
+
+# CHECK: testl $0, %eax
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: movb 0, %al
+0xa0 0x00 0x00 0x00 0x00
+
+# CHECK: movw 0, %ax
+0x66 0xa1 0x00 0x00 0x00 0x00
+
+# CHECK: movl 0, %eax
+0xa1 0x00 0x00 0x00 0x00
+
+# CHECK: movb %al, 0
+0xa2 0x00 0x00 0x00 0x00
+
+# CHECK: movw %ax, 0
+0x66 0xa3 0x00 0x00 0x00 0x00
+
+# CHECK: movl %eax, 0
+0xa3 0x00 0x00 0x00 0x00