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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-09 22:02:17 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-09 22:02:17 +0000 |
| commit | 840bf7eda7c81059a0aae9abd51262147c60d814 (patch) | |
| tree | f61a58655cfe14f77b1f28bacab0daf3360010ab /test | |
| parent | b3e6c70c84214821b4759086519730e68303a455 (diff) | |
| download | llvm-840bf7eda7c81059a0aae9abd51262147c60d814.tar.gz llvm-840bf7eda7c81059a0aae9abd51262147c60d814.tar.bz2 llvm-840bf7eda7c81059a0aae9abd51262147c60d814.tar.xz | |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index eabab5de1b..6dba430a22 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -222,6 +222,7 @@ Lforward: and r6, r7, r8, asr r2 and r6, r7, r8, ror r2 and r10, r1, r6, rrx + and r2, r3, #0x7fffffff @ destination register is optional and r1, #0xf @@ -249,6 +250,7 @@ Lforward: @ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0] @ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0] @ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0] +@ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0] |