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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-21 14:44:37 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-21 14:44:37 +0000 |
| commit | 84569698f01bcb49afe5b6140bf0d61cf4f3cf5a (patch) | |
| tree | ce5b44d09442fcfc6faf259ee486feb918417b86 /test | |
| parent | cab0a1933875935c717136d251e2af9749533ba8 (diff) | |
| download | llvm-84569698f01bcb49afe5b6140bf0d61cf4f3cf5a.tar.gz llvm-84569698f01bcb49afe5b6140bf0d61cf4f3cf5a.tar.bz2 llvm-84569698f01bcb49afe5b6140bf0d61cf4f3cf5a.tar.xz | |
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/PowerPC/ppc64-fixups.s | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index 1c16a97a28..b99bc6202f 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -87,6 +87,32 @@ # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0 ld 1, target@l(3) +# CHECK: ld 1, target(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0 + ld 1, target(3) + +base: +# CHECK: li 3, target-base # encoding: [0x38,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2 + li 3, target-base + +# CHECK: li 3, target-base@h # encoding: [0x38,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target-base@h, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6 + li 3, target-base@h + +# CHECK: li 3, target-base@l # encoding: [0x38,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target-base@l, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA + li 3, target-base@l + +# CHECK: li 3, target-base@ha # encoding: [0x38,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target-base@ha, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE + li 3, target-base@ha + # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] # CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 |