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| author | Diego Novillo <dnovillo@google.com> | 2014-02-13 20:05:03 +0000 |
|---|---|---|
| committer | Diego Novillo <dnovillo@google.com> | 2014-02-13 20:05:03 +0000 |
| commit | 86dd0f939fbd7ccce4c6766bf97d6d48aee91d2f (patch) | |
| tree | b18306864238a07c827604173cc338e538784f62 /test | |
| parent | f2df02b3552dd3ad397362243bf589fdf9c6cc3c (diff) | |
| download | llvm-86dd0f939fbd7ccce4c6766bf97d6d48aee91d2f.tar.gz llvm-86dd0f939fbd7ccce4c6766bf97d6d48aee91d2f.tar.bz2 llvm-86dd0f939fbd7ccce4c6766bf97d6d48aee91d2f.tar.xz | |
Fix generation of 'isa' and 'discriminator' keywords.
Summary:
There should be a space before each of these two keywords to avoid
generating invalid assembly files.
NOTE: I could not find an obvious maintainers in CODE_OWNERS.TXT, but
this seems related to debug info.
Reviewers: echristo
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D2791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201359 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/AsmParser/directive_loc.s | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/test/MC/AsmParser/directive_loc.s b/test/MC/AsmParser/directive_loc.s index 700a32ca38..5a24ae9746 100644 --- a/test/MC/AsmParser/directive_loc.s +++ b/test/MC/AsmParser/directive_loc.s @@ -1,9 +1,18 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s -# FIXME: Actually test the output. +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s -check-prefix=FILE +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s -check-prefix=BASIC-LOC-1 +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s -check-prefix=BASIC-LOC-2 +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s -check-prefix=DISCRIMINATOR +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s -check-prefix=ISA .file 1 "hello" +# FILE: .file 1 "hello" .loc 1 .loc 1 2 +# BASIC-LOC-1: .loc 1 2 0 .loc 1 2 3 +# BASIC-LOC-2: .loc 1 2 3 .loc 1 2 discriminator 1 +# DISCRIMINATOR: 1 2 0 discriminator 1 + .loc 1 2 0 isa 3 +# ISA: 1 2 0 isa 3 .loc 1 0 |