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| author | Tim Northover <tnorthover@apple.com> | 2014-04-22 12:45:42 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-22 12:45:42 +0000 |
| commit | 8b36f98fd5e701b902b2981a324ed014e80fd121 (patch) | |
| tree | 0ca784f307a9ab5fe7d9ec1533879b77ac3d7ff1 /test | |
| parent | c499ecd1d18a75b0ba30c9a7aaecaadd2f782d5d (diff) | |
| download | llvm-8b36f98fd5e701b902b2981a324ed014e80fd121.tar.gz llvm-8b36f98fd5e701b902b2981a324ed014e80fd121.tar.bz2 llvm-8b36f98fd5e701b902b2981a324ed014e80fd121.tar.xz | |
AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206888 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AArch64/fp128.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/logical_shifted_reg.ll | 5 | ||||
| -rw-r--r-- | test/CodeGen/ARM64/fp128.ll | 3 |
3 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/AArch64/fp128.ll b/test/CodeGen/AArch64/fp128.ll index 317470be9d..71c1cfe0e3 100644 --- a/test/CodeGen/AArch64/fp128.ll +++ b/test/CodeGen/AArch64/fp128.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 -; RUN: llc -mtriple=arm64-none-linux-gnu -mcpu=cyclone -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64 - +; arm64 has a separate copy of this test. @lhs = global fp128 zeroinitializer @rhs = global fp128 zeroinitializer @@ -206,8 +205,9 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { %val = select i1 %cond, fp128 %lhs, fp128 %rhs store fp128 %val, fp128* @lhs -; CHECK: cmp {{w[0-9]+}}, #0 +; CHECK-AARCH64: cmp {{w[0-9]+}}, #0 ; CHECK-AARCH64: str q1, [sp] +; CHECK-ARM64: tst {{w[0-9]+}}, #0x1 ; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: BB# ; CHECK-AARCH64-NEXT: str q0, [sp] diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll index a08ba20c7f..49b253bcfd 100644 --- a/test/CodeGen/AArch64/logical_shifted_reg.ll +++ b/test/CodeGen/AArch64/logical_shifted_reg.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu | FileCheck %s @var1_32 = global i32 0 @var2_32 = global i32 0 @@ -6,7 +7,7 @@ @var1_64 = global i64 0 @var2_64 = global i64 0 -define void @logical_32bit() { +define void @logical_32bit() minsize { ; CHECK-LABEL: logical_32bit: %val1 = load i32* @var1_32 %val2 = load i32* @var2_32 @@ -96,7 +97,7 @@ define void @logical_32bit() { ret void } -define void @logical_64bit() { +define void @logical_64bit() minsize { ; CHECK-LABEL: logical_64bit: %val1 = load i64* @var1_64 %val2 = load i64* @var2_64 diff --git a/test/CodeGen/ARM64/fp128.ll b/test/CodeGen/ARM64/fp128.ll index d3ac28c507..a1a956d231 100644 --- a/test/CodeGen/ARM64/fp128.ll +++ b/test/CodeGen/ARM64/fp128.ll @@ -202,8 +202,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { %val = select i1 %cond, fp128 %lhs, fp128 %rhs store fp128 %val, fp128* @lhs, align 16 -; CHECK: and [[BIT:w[0-9]+]], w0, #0x1 -; CHECK: cmp [[BIT]], #0 +; CHECK: tst w0, #0x1 ; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: BB# ; CHECK-NEXT: orr v[[VAL:[0-9]+]].16b, v0.16b, v0.16b |