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authorCraig Topper <craig.topper@gmail.com>2013-10-14 01:42:32 +0000
committerCraig Topper <craig.topper@gmail.com>2013-10-14 01:42:32 +0000
commit8e121843c19297205fe9acb9153570f596838eb9 (patch)
tree0853174a297d18a94cf35753dedfe4b9bf96bfd2 /test
parentbae9f69d37a60aad0185cdf17434ec188c976e67 (diff)
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Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/MC/Disassembler/X86/x86-64.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt
index b9478e8142..8c6bc0e296 100644
--- a/test/MC/Disassembler/X86/x86-64.txt
+++ b/test/MC/Disassembler/X86/x86-64.txt
@@ -235,3 +235,9 @@
# CHECK: movd %xmm0, %rax
0x66 0x48 0x0f 0x7e 0xc0
+
+# CHECK: pextrw $3, %xmm3, %ecx
+0x66 0x0f 0x3a 0x15 0xd9 0x03
+
+# CHECK: pextrw $3, %xmm3, (%rax)
+0x66 0x0f 0x3a 0x15 0x18 0x03