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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-05 03:10:56 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-05 03:10:56 +0000 |
| commit | 9243c4f7c54b8d0be22a4c9d411b15f462039d06 (patch) | |
| tree | 768ec2f4128b47e5a5f7e1557309c3c1664afc1d /test | |
| parent | 63246de68653ce330c55453cf9a18a306a4d2319 (diff) | |
| download | llvm-9243c4f7c54b8d0be22a4c9d411b15f462039d06.tar.gz llvm-9243c4f7c54b8d0be22a4c9d411b15f462039d06.tar.bz2 llvm-9243c4f7c54b8d0be22a4c9d411b15f462039d06.tar.xz | |
Pass the right sign to TLI->isLegalICmpImmediate.
LSR can fold three addressing modes into its ICmpZero node:
ICmpZero BaseReg + Offset => ICmp BaseReg, -Offset
ICmpZero -1*ScaleReg + Offset => ICmp ScaleReg, Offset
ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg
The first two cases are only used if TLI->isLegalICmpImmediate() likes
the offset.
Make sure the right Offset sign is passed to this method in the second
case. The ARM version is not symmetric.
<rdar://problem/11184260>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154079 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/commute-movcc.ll | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/commute-movcc.ll b/test/CodeGen/ARM/commute-movcc.ll index f53ac17876..7316452cd6 100644 --- a/test/CodeGen/ARM/commute-movcc.ll +++ b/test/CodeGen/ARM/commute-movcc.ll @@ -17,7 +17,11 @@ ; CHECK: movls ; CHECK-NOT: mov +; This is really an LSR test: Make sure that cmp is using the incremented +; induction variable. ; CHECK: %if.end8 +; CHECK: add{{(s|\.w)?}} [[IV:r[0-9]+]], {{.*}}#1 +; CHECK: cmp [[IV]], # define i32 @f(i32* nocapture %a, i32 %Pref) nounwind ssp { entry: |