summaryrefslogtreecommitdiff
path: root/test
diff options
context:
space:
mode:
authorMatheus Almeida <matheus.almeida@imgtec.com>2014-06-18 17:10:30 +0000
committerMatheus Almeida <matheus.almeida@imgtec.com>2014-06-18 17:10:30 +0000
commit95f1fa7ec339f1dc27e279a2241420c4db850f5b (patch)
treed1fb701db003b91bfc22a058afdfae8324bb3c4a /test
parenta841620f66f2e5673a0a0529f655dcb742031e6b (diff)
downloadllvm-95f1fa7ec339f1dc27e279a2241420c4db850f5b.tar.gz
llvm-95f1fa7ec339f1dc27e279a2241420c4db850f5b.tar.bz2
llvm-95f1fa7ec339f1dc27e279a2241420c4db850f5b.tar.xz
[mips] SYNC $stype instruction was added in Mips32
but SYNC with an implied operand ($stype = 0) is valid since Mips2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211185 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Mips/atomic.ll4
-rw-r--r--test/MC/Mips/mips1/invalid-mips2.s1
-rw-r--r--test/MC/Mips/mips1/invalid-mips32.s10
-rw-r--r--test/MC/Mips/mips2/invalid-mips32.s2
-rw-r--r--test/MC/Mips/mips2/valid.s1
-rw-r--r--test/MC/Mips/mips3/invalid-mips32.s10
-rw-r--r--test/MC/Mips/mips3/valid.s1
-rw-r--r--test/MC/Mips/mips32/valid.s2
-rw-r--r--test/MC/Mips/mips32r2/valid.s2
-rw-r--r--test/MC/Mips/mips32r6/valid.s2
-rw-r--r--test/MC/Mips/mips4/invalid-mips32.s10
-rw-r--r--test/MC/Mips/mips4/valid.s1
-rw-r--r--test/MC/Mips/mips5/invalid-mips32.s10
-rw-r--r--test/MC/Mips/mips5/valid.s1
-rw-r--r--test/MC/Mips/mips64/valid.s2
-rw-r--r--test/MC/Mips/mips64r2/valid.s2
-rw-r--r--test/MC/Mips/mips64r6/valid.s2
17 files changed, 61 insertions, 2 deletions
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index 20d46708c5..066d42cc30 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -344,11 +344,11 @@ entry:
; ALL-LABEL: CheckSync:
-; ALL: sync 0
+; ALL: sync
; ALL: ll
; ALL: sc
; ALL: beq
-; ALL: sync 0
+; ALL: sync
}
; make sure that this assertion in
diff --git a/test/MC/Mips/mips1/invalid-mips2.s b/test/MC/Mips/mips1/invalid-mips2.s
index 6c3e80ac45..7db261d42c 100644
--- a/test/MC/Mips/mips1/invalid-mips2.s
+++ b/test/MC/Mips/mips1/invalid-mips2.s
@@ -21,3 +21,4 @@
tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips1/invalid-mips32.s b/test/MC/Mips/mips1/invalid-mips32.s
new file mode 100644
index 0000000000..4ad8d63eb2
--- /dev/null
+++ b/test/MC/Mips/mips1/invalid-mips32.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips2/invalid-mips32.s b/test/MC/Mips/mips2/invalid-mips32.s
index 653d2a1311..43ea345441 100644
--- a/test/MC/Mips/mips2/invalid-mips32.s
+++ b/test/MC/Mips/mips2/invalid-mips32.s
@@ -40,3 +40,5 @@
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s
index d4f48ec8d6..9c3706ee3f 100644
--- a/test/MC/Mips/mips2/valid.s
+++ b/test/MC/Mips/mips2/valid.s
@@ -122,6 +122,7 @@
swc3 $10,-32265($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips3/invalid-mips32.s b/test/MC/Mips/mips3/invalid-mips32.s
new file mode 100644
index 0000000000..3acd7651e6
--- /dev/null
+++ b/test/MC/Mips/mips3/invalid-mips32.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index a68dc91420..cb209fdb20 100644
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -179,6 +179,7 @@
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s
index 68db86e91c..c58cb88b05 100644
--- a/test/MC/Mips/mips32/valid.s
+++ b/test/MC/Mips/mips32/valid.s
@@ -147,6 +147,8 @@
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3)
swr $s1,-26590($14)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s
index b92facf666..e152f6f437 100644
--- a/test/MC/Mips/mips32r2/valid.s
+++ b/test/MC/Mips/mips32r2/valid.s
@@ -177,6 +177,8 @@
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s
index b0f0b5c482..0766079fda 100644
--- a/test/MC/Mips/mips32r6/valid.s
+++ b/test/MC/Mips/mips32r6/valid.s
@@ -147,3 +147,5 @@
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
diff --git a/test/MC/Mips/mips4/invalid-mips32.s b/test/MC/Mips/mips4/invalid-mips32.s
new file mode 100644
index 0000000000..52dea02d10
--- /dev/null
+++ b/test/MC/Mips/mips4/invalid-mips32.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s
index 2086a12602..949b91da92 100644
--- a/test/MC/Mips/mips4/valid.s
+++ b/test/MC/Mips/mips4/valid.s
@@ -198,6 +198,7 @@
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips5/invalid-mips32.s b/test/MC/Mips/mips5/invalid-mips32.s
new file mode 100644
index 0000000000..2e2c8da462
--- /dev/null
+++ b/test/MC/Mips/mips5/invalid-mips32.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+
+ sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s
index 3f350b1d36..3afdee1887 100644
--- a/test/MC/Mips/mips5/valid.s
+++ b/test/MC/Mips/mips5/valid.s
@@ -200,6 +200,7 @@
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s
index 3f4149a8f5..81c2268779 100644
--- a/test/MC/Mips/mips64/valid.s
+++ b/test/MC/Mips/mips64/valid.s
@@ -214,6 +214,8 @@
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s
index df144921a7..3d85c137ab 100644
--- a/test/MC/Mips/mips64r2/valid.s
+++ b/test/MC/Mips/mips64r2/valid.s
@@ -241,6 +241,8 @@
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s
index c16752f7fb..9f32562191 100644
--- a/test/MC/Mips/mips64r6/valid.s
+++ b/test/MC/Mips/mips64r6/valid.s
@@ -165,3 +165,5 @@
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-29 13:19:05 +0000