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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-06-26 18:48:17 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-06-26 18:48:17 +0000 |
| commit | 9a308df027b60057d0fe3ba7a3ee9648f6677879 (patch) | |
| tree | ab9099f616eb3dfee3cd5db7f6f79c203e549f45 /test | |
| parent | a8f936446134c9cdcf06f74b861112a62fe66d71 (diff) | |
| download | llvm-9a308df027b60057d0fe3ba7a3ee9648f6677879.tar.gz llvm-9a308df027b60057d0fe3ba7a3ee9648f6677879.tar.bz2 llvm-9a308df027b60057d0fe3ba7a3ee9648f6677879.tar.xz | |
[mips] Improve code generation for constant multiplication using shifts, adds and
subs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/const-mult.ll | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll new file mode 100644 index 0000000000..d818044dec --- /dev/null +++ b/test/CodeGen/Mips/const-mult.ll @@ -0,0 +1,49 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64 + +; CHECK: mul5_32: +; CHECK: sll $[[R0:[0-9]+]], $4, 2 +; CHECK: addu ${{[0-9]+}}, $[[R0]], $4 + +define i32 @mul5_32(i32 %a) { +entry: + %mul = mul nsw i32 %a, 5 + ret i32 %mul +} + +; CHECK: mul27_32: +; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2 +; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4 +; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5 +; CHECK: subu ${{[0-9]+}}, $[[R2]], $[[R1]] + +define i32 @mul27_32(i32 %a) { +entry: + %mul = mul nsw i32 %a, 27 + ret i32 %mul +} + +; CHECK: muln2147483643_32: +; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2 +; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4 +; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31 +; CHECK: addu ${{[0-9]+}}, $[[R2]], $[[R1]] + +define i32 @muln2147483643_32(i32 %a) { +entry: + %mul = mul nsw i32 %a, -2147483643 + ret i32 %mul +} + +; CHECK64: muln9223372036854775805_64: +; CHECK64-DAG: sll $[[R0:[0-9]+]], $4, 1 +; CHECK64-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4 +; CHECK64-DAG: sll $[[R2:[0-9]+]], $4, 63 +; CHECK64: addu ${{[0-9]+}}, $[[R2]], $[[R1]] + +define i64 @muln9223372036854775805_64(i64 %a) { +entry: + %mul = mul nsw i64 %a, -9223372036854775805 + ret i64 %mul +} |