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author | Evan Cheng <evan.cheng@apple.com> | 2008-11-18 22:28:38 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-11-18 22:28:38 +0000 |
commit | 9c64bf3905ea338719800008c03d95a17cb26689 (patch) | |
tree | d07c869468a85a30bd9dca114fef35d03ef0b937 /test | |
parent | 01f63cdb0433fd2e4b76538ee58ee89c26349564 (diff) | |
download | llvm-9c64bf3905ea338719800008c03d95a17cb26689.tar.gz llvm-9c64bf3905ea338719800008c03d95a17cb26689.tar.bz2 llvm-9c64bf3905ea338719800008c03d95a17cb26689.tar.xz |
Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll b/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll new file mode 100644 index 0000000000..164e9643f1 --- /dev/null +++ b/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 + +define hidden i64 @__muldi3(i64 %u, i64 %v) nounwind { +entry: + %0 = trunc i64 %u to i32 ; <i32> [#uses=1] + %asmtmp = tail call { i32, i32, i32, i32, i32 } asm "@ Inlined umul_ppmm\0A\09mov\09$2, $5, lsr #16\0A\09mov\09$0, $6, lsr #16\0A\09bic\09$3, $5, $2, lsl #16\0A\09bic\09$4, $6, $0, lsl #16\0A\09mul\09$1, $3, $4\0A\09mul\09$4, $2, $4\0A\09mul\09$3, $0, $3\0A\09mul\09$0, $2, $0\0A\09adds\09$3, $4, $3\0A\09addcs\09$0, $0, #65536\0A\09adds\09$1, $1, $3, lsl #16\0A\09adc\09$0, $0, $3, lsr #16", "=&r,=r,=&r,=&r,=r,r,r,~{cc}"(i32 %0, i32 0) nounwind ; <{ i32, i32, i32, i32, i32 }> [#uses=1] + %asmresult1 = extractvalue { i32, i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1] + %asmresult116 = zext i32 %asmresult1 to i64 ; <i64> [#uses=1] + %asmresult116.ins = or i64 0, %asmresult116 ; <i64> [#uses=1] + %1 = lshr i64 %v, 32 ; <i64> [#uses=1] + %2 = mul i64 %1, %u ; <i64> [#uses=1] + %3 = add i64 %2, 0 ; <i64> [#uses=1] + %4 = shl i64 %3, 32 ; <i64> [#uses=1] + %5 = add i64 %asmresult116.ins, %4 ; <i64> [#uses=1] + ret i64 %5 +} |