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| author | Jim Grosbach <grosbach@apple.com> | 2010-09-17 21:58:46 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-17 21:58:46 +0000 |
| commit | 9ce75625ebb43e9b4fa2a1f7a8611f07640bbe2b (patch) | |
| tree | 29c21d12e3c168895df12786e2ed430b237c5e08 /test | |
| parent | f437f733484169cf67f7c3e798908bbf27175580 (diff) | |
| download | llvm-9ce75625ebb43e9b4fa2a1f7a8611f07640bbe2b.tar.gz llvm-9ce75625ebb43e9b4fa2a1f7a8611f07640bbe2b.tar.bz2 llvm-9ce75625ebb43e9b4fa2a1f7a8611f07640bbe2b.tar.xz | |
Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/bfi.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ispositive.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/long_shift.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/ARM/mul_const.ll | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index 59e2b43a91..0e36283a39 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -19,7 +19,7 @@ entry: define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize { entry: ; CHECK: f2 -; CHECK: mov r1, r1, lsr #7 +; CHECK: lsr{{.*}}#7 ; CHECK: bfi r0, r1, #7, #16 %and = and i32 %A, -8388481 ; <i32> [#uses=1] %and2 = and i32 %B, 8388480 ; <i32> [#uses=1] @@ -30,7 +30,7 @@ entry: define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { entry: ; CHECK: f3 -; CHECK: mov r2, r0, lsr #7 +; CHECK: lsr{{.*}} #7 ; CHECK: mov r0, r1 ; CHECK: bfi r0, r2, #7, #16 %and = and i32 %A, 8388480 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ispositive.ll b/test/CodeGen/ARM/ispositive.ll index 245ed516f7..2f1a2cfd77 100644 --- a/test/CodeGen/ARM/ispositive.ll +++ b/test/CodeGen/ARM/ispositive.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i32 @test1(i32 %X) { -; CHECK: mov r0, r0, lsr #31 +; CHECK: lsr{{.*}}#31 entry: icmp slt i32 %X, 0 ; <i1>:0 [#uses=1] zext i1 %0 to i32 ; <i32>:1 [#uses=1] diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 1ec4d15f66..43d58ecbd4 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -14,7 +14,7 @@ define i64 @f0(i64 %A, i64 %B) { define i32 @f1(i64 %x, i64 %y) { ; CHECK: f1 -; CHECK: mov r0, r0, lsl r2 +; CHECK: lsl{{.*}}r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b @@ -22,7 +22,7 @@ define i32 @f1(i64 %x, i64 %y) { define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 @@ -34,7 +34,7 @@ define i32 @f2(i64 %x, i64 %y) { define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll index 8c10246461..3cb8a8e816 100644 --- a/test/CodeGen/ARM/mul_const.ll +++ b/test/CodeGen/ARM/mul_const.ll @@ -36,7 +36,7 @@ define i32 @t12288(i32 %v) nounwind readnone { entry: ; CHECK: t12288: ; CHECK: add r0, r0, r0, lsl #1 -; CHECK: mov r0, r0, lsl #12 +; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, 12288 ret i32 %0 } |