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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2014-02-02 03:12:34 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2014-02-02 03:12:34 +0000 |
| commit | a16c1b55e2aac49c7336f3f54b50bbe85335712e (patch) | |
| tree | 2cc6f130fcbdbcba7aa30ad45315a1e519c954a7 /test | |
| parent | 1bdadf38ef3273b40c2f7f253157a09a975f08a3 (diff) | |
| download | llvm-a16c1b55e2aac49c7336f3f54b50bbe85335712e.tar.gz llvm-a16c1b55e2aac49c7336f3f54b50bbe85335712e.tar.bz2 llvm-a16c1b55e2aac49c7336f3f54b50bbe85335712e.tar.xz | |
LoopVectorizer: Enable unrolling of conditional stores and the load/store
unrolling heuristic per default
Benchmarking on x86_64 (thanks Chandler!) and ARM has shown those options speed
up some benchmarks while not causing any interesting regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200621 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/Transforms/LoopVectorize/ARM/arm-unroll.ll | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll index 0b87e0e740..8843fc2d2b 100644 --- a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll +++ b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll @@ -47,6 +47,7 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) { %sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ] %sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ] %sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ] + %sum.06 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] %2 = getelementptr inbounds i32* %A, i32 %i.02 %3 = load i32* %2, align 4 %4 = add nsw i32 %3, %sum.01 @@ -55,6 +56,7 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) { %7 = add nsw i32 %3, %sum.03 %8 = add nsw i32 %3, %sum.04 %9 = add nsw i32 %3, %sum.05 + %10 = add nsw i32 %3, %sum.05 %exitcond = icmp eq i32 %5, %n br i1 %exitcond, label %._crit_edge, label %.lr.ph @@ -64,5 +66,6 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) { %sum.2.lcssa = phi i32 [ 0, %0 ], [ %7, %.lr.ph ] %sum.4.lcssa = phi i32 [ 0, %0 ], [ %8, %.lr.ph ] %sum.5.lcssa = phi i32 [ 0, %0 ], [ %9, %.lr.ph ] + %sum.6.lcssa = phi i32 [ 0, %0 ], [ %10, %.lr.ph ] ret i32 %sum.0.lcssa } |