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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-12 04:36:01 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-12 04:36:01 +0000 |
| commit | a2fce1169d8696f9950a17b1f85126b08c863154 (patch) | |
| tree | 7f5114b1d286e80a80e681cdd174507ec9d7860b /test | |
| parent | 188fbacade4772757363045ab417927d525e57f6 (diff) | |
| download | llvm-a2fce1169d8696f9950a17b1f85126b08c863154.tar.gz llvm-a2fce1169d8696f9950a17b1f85126b08c863154.tar.bz2 llvm-a2fce1169d8696f9950a17b1f85126b08c863154.tar.xz | |
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings. Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.
An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero. By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/arm_addrmode2.s | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/addrmode2-reencoding.txt | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s index a4fb9356db..53290ab0dd 100644 --- a/test/MC/ARM/arm_addrmode2.s +++ b/test/MC/ARM/arm_addrmode2.s @@ -4,19 +4,19 @@ @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6] @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4] -@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4] +@ CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4] @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6] @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6] @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4] -@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4] +@ CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4] @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6] @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6] @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4] -@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4] +@ CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4] @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6] @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6] @ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4] -@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4] +@ CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4] ldrt r1, [r0], r2 ldrt r1, [r0], r2, lsr #3 ldrt r1, [r0], #4 diff --git a/test/MC/Disassembler/ARM/addrmode2-reencoding.txt b/test/MC/Disassembler/ARM/addrmode2-reencoding.txt index 128b4b971c..08d2de687a 100644 --- a/test/MC/Disassembler/ARM/addrmode2-reencoding.txt +++ b/test/MC/Disassembler/ARM/addrmode2-reencoding.txt @@ -5,8 +5,8 @@ 0x00 0x10 0xa0 0xe4 0x00 0x10 0xe0 0xe4 -# CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4] -# CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4] -# CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4] -# CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4] +# CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4] +# CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4] +# CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4] +# CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4] |