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author | Hao Liu <Hao.Liu@arm.com> | 2013-12-09 03:51:42 +0000 |
---|---|---|
committer | Hao Liu <Hao.Liu@arm.com> | 2013-12-09 03:51:42 +0000 |
commit | a339740cb86e49a3300979b16f8c05df43bce637 (patch) | |
tree | 789c1b2e1d6d855e51ef4a507a861468a5e48727 /test | |
parent | 2f3f02f6f531d1bf8f775f3556c37ccacd3b6133 (diff) | |
download | llvm-a339740cb86e49a3300979b16f8c05df43bce637.tar.gz llvm-a339740cb86e49a3300979b16f8c05df43bce637.tar.bz2 llvm-a339740cb86e49a3300979b16f8c05df43bce637.tar.xz |
[AArch64]Add missing pair intrinsics such as:
int32_t vminv_s32(int32x2_t a)
which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196749 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/AArch64/neon-add-pairwise.ll | 9 | ||||
-rw-r--r-- | test/CodeGen/AArch64/neon-max-min-pairwise.ll | 36 | ||||
-rw-r--r-- | test/CodeGen/AArch64/neon-misc.ll | 21 |
3 files changed, 65 insertions, 1 deletions
diff --git a/test/CodeGen/AArch64/neon-add-pairwise.ll b/test/CodeGen/AArch64/neon-add-pairwise.ll index 1abfed3190..32d8222ded 100644 --- a/test/CodeGen/AArch64/neon-add-pairwise.ll +++ b/test/CodeGen/AArch64/neon-add-pairwise.ll @@ -90,3 +90,12 @@ define <2 x double> @test_faddp_v2f64(<2 x double> %lhs, <2 x double> %rhs) { ret <2 x double> %val } +define i32 @test_vaddv.v2i32(<2 x i32> %a) { +; CHECK-LABEL: test_vaddv.v2i32 +; CHECK: addp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + %1 = tail call <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i32> %1, i32 0 + ret i32 %2 +} + +declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>)
\ No newline at end of file diff --git a/test/CodeGen/AArch64/neon-max-min-pairwise.ll b/test/CodeGen/AArch64/neon-max-min-pairwise.ll index d757aca86a..3e18077337 100644 --- a/test/CodeGen/AArch64/neon-max-min-pairwise.ll +++ b/test/CodeGen/AArch64/neon-max-min-pairwise.ll @@ -308,3 +308,39 @@ define <2 x double> @test_fminnmp_v2f64(<2 x double> %lhs, <2 x double> %rhs) { ret <2 x double> %val } +define i32 @test_vminv_s32(<2 x i32> %a) { +; CHECK-LABEL: test_vminv_s32 +; CHECK: sminp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + %1 = tail call <1 x i32> @llvm.aarch64.neon.sminv.v1i32.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i32> %1, i32 0 + ret i32 %2 +} + +define i32 @test_vminv_u32(<2 x i32> %a) { +; CHECK-LABEL: test_vminv_u32 +; CHECK: uminp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + %1 = tail call <1 x i32> @llvm.aarch64.neon.uminv.v1i32.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i32> %1, i32 0 + ret i32 %2 +} + +define i32 @test_vmaxv_s32(<2 x i32> %a) { +; CHECK-LABEL: test_vmaxv_s32 +; CHECK: smaxp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + %1 = tail call <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i32> %1, i32 0 + ret i32 %2 +} + +define i32 @test_vmaxv_u32(<2 x i32> %a) { +; CHECK-LABEL: test_vmaxv_u32 +; CHECK: umaxp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + %1 = tail call <1 x i32> @llvm.aarch64.neon.umaxv.v1i32.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i32> %1, i32 0 + ret i32 %2 +} + +declare <1 x i32> @llvm.aarch64.neon.uminv.v1i32.v2i32(<2 x i32>) +declare <1 x i32> @llvm.aarch64.neon.sminv.v1i32.v2i32(<2 x i32>) +declare <1 x i32> @llvm.aarch64.neon.umaxv.v1i32.v2i32(<2 x i32>) +declare <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32>)
\ No newline at end of file diff --git a/test/CodeGen/AArch64/neon-misc.ll b/test/CodeGen/AArch64/neon-misc.ll index 9660bf2c7a..851a2f364c 100644 --- a/test/CodeGen/AArch64/neon-misc.ll +++ b/test/CodeGen/AArch64/neon-misc.ll @@ -1796,4 +1796,23 @@ declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>) declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>) declare <1 x double> @llvm.sqrt.v1f64(<1 x double>) declare <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double>) -declare <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double>)
\ No newline at end of file +declare <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double>) + +define i64 @test_vaddlv_s32(<2 x i32> %a) { +; CHECK-LABEL: test_vaddlv_s32 +; CHECK: saddlp {{v[0-9]+}}.1d, {{v[0-9]+}}.2s + %1 = tail call <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i64> %1, i32 0 + ret i64 %2 +} + +define i64 @test_vaddlv_u32(<2 x i32> %a) { +; CHECK-LABEL: test_vaddlv_u32 +; CHECK: uaddlp {{v[0-9]+}}.1d, {{v[0-9]+}}.2s + %1 = tail call <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32> %a) + %2 = extractelement <1 x i64> %1, i32 0 + ret i64 %2 +} + +declare <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32>) +declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>)
\ No newline at end of file |