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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-09 21:28:25 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-09 21:28:25 +0000 |
| commit | a4e3c7fc4ba2d55695b0484480685698132eba20 (patch) | |
| tree | da03cd56d7e4b45f98cf306a5f3214c45287b959 /test | |
| parent | 2fac1d5d61a83c45dcf44119c41dce15ef10e9dc (diff) | |
| download | llvm-a4e3c7fc4ba2d55695b0484480685698132eba20.tar.gz llvm-a4e3c7fc4ba2d55695b0484480685698132eba20.tar.bz2 llvm-a4e3c7fc4ba2d55695b0484480685698132eba20.tar.xz | |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/neon-vld-encoding.s | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index 8eeb865bcb..e7e0f3fdb8 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -118,6 +118,20 @@ vld2.16 {d16, d17, d18, d19}, [r0, :128] vld2.32 {d16, d17, d18, d19}, [r0, :256] + vld2.8 {d19, d20}, [r0, :64]! + vld2.16 {d16, d17}, [r0, :128]! + vld2.32 {q10}, [r0]! + vld2.8 {d4-d7}, [r0, :64]! + vld2.16 {d1, d2, d3, d4}, [r0, :128]! + vld2.32 {q7, q8}, [r0, :256]! + + vld2.8 {d19, d20}, [r0, :64], r6 + vld2.16 {d16, d17}, [r0, :128], r6 + vld2.32 {q10}, [r0], r6 + vld2.8 {d4-d7}, [r0, :64], r6 + vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 + vld2.32 {q7, q8}, [r0, :256], r6 + @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] @@ -125,6 +139,20 @@ @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] +@ CHECK: vld2.8 {d19, d20}, [r0, :64]! @ encoding: [0x1d,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x08,0x60,0xf4] +@ CHECK: vld2.32 {d20, d21}, [r0]! @ encoding: [0x8d,0x48,0x60,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64]! @ encoding: [0x1d,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128]! @ encoding: [0x6d,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256]! @ encoding: [0xbd,0xe3,0x20,0xf4] + +@ CHECK: vld2.8 {d19, d20}, [r0, :64], r6 @ encoding: [0x16,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0, :128], r6 @ encoding: [0x66,0x08,0x60,0xf4] +@ CHECK: vld2.32 {d20, d21}, [r0], r6 @ encoding: [0x86,0x48,0x60,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64], r6 @ encoding: [0x16,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 @ encoding: [0x66,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4] + @ vld3.8 {d16, d17, d18}, [r0, :64] @ vld3.16 {d16, d17, d18}, [r0] |