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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-01-22 21:34:25 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-01-22 21:34:25 +0000 |
| commit | a88322c283a001019bd5cd4ddeafc425cc4d00af (patch) | |
| tree | 057a50a20ccbc0fbaec171c93ed39431845013d4 /test | |
| parent | defaca00b8087d452df2b783250a48a32658a910 (diff) | |
| download | llvm-a88322c283a001019bd5cd4ddeafc425cc4d00af.tar.gz llvm-a88322c283a001019bd5cd4ddeafc425cc4d00af.tar.bz2 llvm-a88322c283a001019bd5cd4ddeafc425cc4d00af.tar.xz | |
[mips] Implement MipsRegisterInfo::getRegPressureLimit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/i64arg.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/o32_cc_byval.ll | 10 | ||||
| -rw-r--r-- | test/CodeGen/Mips/tls.ll | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index e16e126af4..201252487e 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -17,9 +17,9 @@ entry: ; CHECK: jalr $25 tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind %sub = add nsw i32 %i, -1 +; CHECK: lw $25, %call16(ff3) ; CHECK: sw $[[R1]], 28($sp) ; CHECK: sw $[[R0]], 24($sp) -; CHECK: lw $25, %call16(ff3) ; CHECK: or $6, $[[R2]], $zero ; CHECK: or $7, $[[R3]], $zero ; CHECK: jalr $25 diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index 5558ba6e10..0a8f85f482 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -12,20 +12,20 @@ define void @f1() nounwind { entry: ; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1) ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) +; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) +; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) +; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) ; CHECK: sw $[[R6]], 36($sp) -; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: sw $[[R5]], 32($sp) -; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) ; CHECK: sw $[[R4]], 28($sp) -; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) ; CHECK: sw $[[R3]], 24($sp) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) ; CHECK: sw $[[R7]], 20($sp) ; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: sw $[[R2]], 16($sp) -; CHECK: lw $7, 4($[[R0]]) ; CHECK: lw $6, %lo(f1.s1)($[[R1]]) +; CHECK: lw $7, 4($[[R0]]) %agg.tmp10 = alloca %struct.S3, align 4 call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind call void @callee2(%struct.S2* byval @f1.s2) nounwind diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 72d30dc369..b86d25e5e5 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -21,9 +21,9 @@ entry: ; PIC: jalr $25 ; PIC: lw $2, 0($2) -; STATIC: rdhwr $3, $29 ; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1) ; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) +; STATIC: rdhwr $3, $29 ; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]] ; STATIC: lw $2, 0($[[R2]]) } |