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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-19 02:34:32 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-19 02:34:32 +0000 |
| commit | ac81cc3282750d724f824547bc519caec0a01bce (patch) | |
| tree | 48f285432c176d1b7a400213c23f69059aecbab3 /test | |
| parent | 565bdbf598d92e86ccf526a151892e3171846650 (diff) | |
| download | llvm-ac81cc3282750d724f824547bc519caec0a01bce.tar.gz llvm-ac81cc3282750d724f824547bc519caec0a01bce.tar.bz2 llvm-ac81cc3282750d724f824547bc519caec0a01bce.tar.xz | |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/PowerPC/stwux.ll | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/stwux.ll b/test/CodeGen/PowerPC/stwux.ll new file mode 100644 index 0000000000..737e9d9f0e --- /dev/null +++ b/test/CodeGen/PowerPC/stwux.ll @@ -0,0 +1,47 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc < %s | FileCheck %s + +@multvec_i = external unnamed_addr global [100 x i32], align 4 + +define fastcc void @subs_STMultiExceptIntern() nounwind { +entry: + br i1 undef, label %while.body.lr.ph, label %return + +while.body.lr.ph: ; preds = %entry + br label %while.body + +while.body: ; preds = %if.end12, %while.body.lr.ph + %i.0240 = phi i32 [ -1, %while.body.lr.ph ], [ %i.1, %if.end12 ] + br i1 undef, label %if.end12, label %if.then + +if.then: ; preds = %while.body + br label %if.end12 + +if.end12: ; preds = %if.then, %while.body + %i.1 = phi i32 [ %i.0240, %while.body ], [ undef, %if.then ] + br i1 undef, label %while.body, label %while.end + +while.end: ; preds = %if.end12 + br i1 undef, label %return, label %if.end15 + +if.end15: ; preds = %while.end + %idxprom.i.i230 = sext i32 %i.1 to i64 + %arrayidx18 = getelementptr inbounds [100 x i32]* @multvec_i, i64 0, i64 %idxprom.i.i230 + store i32 0, i32* %arrayidx18, align 4 + br i1 undef, label %while.body21, label %while.end90 + +while.body21: ; preds = %if.end15 + unreachable + +while.end90: ; preds = %if.end15 + store i32 0, i32* %arrayidx18, align 4 + br label %return + +return: ; preds = %while.end90, %while.end, %entry + ret void + +; CHECK: @subs_STMultiExceptIntern +; CHECK: stwux +} + |