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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-03-31 23:26:08 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-03-31 23:26:08 +0000 |
commit | ae0855401b8c80f96904b6808b0bc4c89216aecd (patch) | |
tree | 9af5d7fbc7585b1555b09e35457b11f4ae9a897f /test | |
parent | 842759662ba3eae35d6078643983a07266be9aa5 (diff) | |
download | llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.gz llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.bz2 llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.xz |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/MC/ARM/arm_addrmode2.s | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s new file mode 100644 index 0000000000..ca99233b9b --- /dev/null +++ b/test/MC/ARM/arm_addrmode2.s @@ -0,0 +1,34 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s + +@ Post-indexed +@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] +@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6] +@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4] +@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6] +@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6] +@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4] +@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6] +@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6] +@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4] +@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6] +@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6] +@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4] + ldrt r1, [r0], r2 + ldrt r1, [r0], r2, lsr #3 + ldrt r1, [r0], #4 + ldrbt r1, [r0], r2 + ldrbt r1, [r0], r2, lsr #3 + ldrbt r1, [r0], #4 + strt r1, [r0], r2 + strt r1, [r0], r2, lsr #3 + strt r1, [r0], #4 + strbt r1, [r0], r2 + strbt r1, [r0], r2, lsr #3 + strbt r1, [r0], #4 + +@ Pre-indexed +@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7] +@ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7] + ldr r1, [r0, r2, lsr #3]! + ldrb r1, [r0, r2, lsr #3]! + |