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authorDan Gohman <gohman@apple.com>2009-10-16 20:59:35 +0000
committerDan Gohman <gohman@apple.com>2009-10-16 20:59:35 +0000
commitb00f236b03ea57520f94823780896ebdbc5d8bdc (patch)
treed023b7481f8606f36efb2bf30f796d830a7eb2f3 /test
parenta43d46f523dff4b784ee28a3b196a065a15d90f2 (diff)
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Move zext and sext casts fed by loads into the same block as the
load, to help SelectionDAG fold them into the loads, unless conditions are unfavorable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84271 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/codegen-prepare-extload.ll20
-rw-r--r--test/CodeGen/X86/stack-color-with-reg.ll4
2 files changed, 22 insertions, 2 deletions
diff --git a/test/CodeGen/X86/codegen-prepare-extload.ll b/test/CodeGen/X86/codegen-prepare-extload.ll
new file mode 100644
index 0000000000..9f57d53178
--- /dev/null
+++ b/test/CodeGen/X86/codegen-prepare-extload.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; rdar://7304838
+
+; CodeGenPrepare should move the zext into the block with the load
+; so that SelectionDAG can select it with the load.
+
+; CHECK: movzbl (%rdi), %eax
+
+define void @foo(i8* %p, i32* %q) {
+entry:
+ %t = load i8* %p
+ %a = icmp slt i8 %t, 20
+ br i1 %a, label %true, label %false
+true:
+ %s = zext i8 %t to i32
+ store i32 %s, i32* %q
+ ret void
+false:
+ ret void
+}
diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll
index 672f77eef0..0f32a50fc5 100644
--- a/test/CodeGen/X86/stack-color-with-reg.ll
+++ b/test/CodeGen/X86/stack-color-with-reg.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
-; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5
-; RUN: grep asm-printer %t | grep 179
+; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6
+; RUN: grep asm-printer %t | grep 177
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1