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| author | Kevin Enderby <enderby@apple.com> | 2012-04-11 22:40:17 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-04-11 22:40:17 +0000 |
| commit | b318cc16c9e959adb96294b3aa4940e74f68dde3 (patch) | |
| tree | 53d9fab1602828229832382e0dd2b4842837d61c /test | |
| parent | 056c51e59820c4c36d3b9d2f22acb6fd121b798e (diff) | |
| download | llvm-b318cc16c9e959adb96294b3aa4940e74f68dde3.tar.gz llvm-b318cc16c9e959adb96294b3aa4940e74f68dde3.tar.bz2 llvm-b318cc16c9e959adb96294b3aa4940e74f68dde3.tar.xz | |
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 0000000000..8ff3a2b9bd --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 |