Merge all tls tests to two files. One for normal codegen (initial and local

exec) and one for PIC codegen (local and general dynamic).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197081 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 73 insertions, 95 deletions

diff --git a/test/CodeGen/PowerPC/tls-gd.ll b/test/CodeGen/PowerPC/tls-gd.ll
deleted file mode 100644
index 5f0ef9a050..0000000000
--- a/test/CodeGen/PowerPC/tls-gd.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage using
-; the general dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@a = thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32* @a, align 4
-  ret i32 %0
-}
-
-; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsgd@ha
-; CHECK-NEXT: addi 3, [[REG]], a@got@tlsgd@l
-; CHECK:      bl __tls_get_addr(a@tlsgd)
-; CHECK-NEXT: nop
-
diff --git a/test/CodeGen/PowerPC/tls-ie.ll b/test/CodeGen/PowerPC/tls-ie.ll
deleted file mode 100644
index c5cfba7b3f..0000000000
--- a/test/CodeGen/PowerPC/tls-ie.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 <%s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage
-; using the initial-exec model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@a = external thread_local global i32
-
-define signext i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32* @a, align 4
-  ret i32 %0
-}
-
-; CHECK: addis [[REG1:[0-9]+]], 2, a@got@tprel@ha
-; CHECK: ld [[REG2:[0-9]+]], a@got@tprel@l([[REG1]])
-; CHECK: add {{[0-9]+}}, [[REG2]], a@tls
-
diff --git a/test/CodeGen/PowerPC/tls-ld-2.ll b/test/CodeGen/PowerPC/tls-ld-2.ll
deleted file mode 100644
index 4399b330ea..0000000000
--- a/test/CodeGen/PowerPC/tls-ld-2.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck %s
-
-; Test peephole optimization for thread-local storage using the
-; local dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@a = hidden thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32* @a, align 4
-  ret i32 %0
-}
-
-; CHECK:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
-; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l
-; CHECK:      bl __tls_get_addr(a@tlsld)
-; CHECK-NEXT: nop
-; CHECK:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
-; CHECK-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
diff --git a/test/CodeGen/PowerPC/tls-ld.ll b/test/CodeGen/PowerPC/tls-ld.ll
deleted file mode 100644
index db02a56f6a..0000000000
--- a/test/CodeGen/PowerPC/tls-ld.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage using
-; the local dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@a = hidden thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
-  %retval = alloca i32, align 4
-  store i32 0, i32* %retval
-  %0 = load i32* @a, align 4
-  ret i32 %0
-}
-
-; CHECK:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
-; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l
-; CHECK:      bl __tls_get_addr(a@tlsld)
-; CHECK-NEXT: nop
-; CHECK:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
-; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll
new file mode 100644
index 0000000000..7c9433fb01
--- /dev/null
+++ b/test/CodeGen/PowerPC/tls-pic.ll
@@ -0,0 +1,54 @@
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s
+
+; Test correct assembly code generation for thread-local storage using
+; the local dynamic model.
+
+@a = hidden thread_local global i32 0, align 4
+
+define signext i32 @main() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* @a, align 4
+  ret i32 %0
+}
+
+; OPT0-LABEL: main:
+; OPT0:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
+; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l
+; OPT0:      bl __tls_get_addr(a@tlsld)
+; OPT0-NEXT: nop
+; OPT0:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
+; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
+
+; Test peephole optimization for thread-local storage using the
+; local dynamic model.
+
+; OPT1-LABEL: main:
+; OPT1:      addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
+; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l
+; OPT1:      bl __tls_get_addr(a@tlsld)
+; OPT1-NEXT: nop
+; OPT1:      addis [[REG2:[0-9]+]], 3, a@dtprel@ha
+; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
+
+; Test correct assembly code generation for thread-local storage using
+; the general dynamic model.
+
+@a2 = thread_local global i32 0, align 4
+
+define signext i32 @main2() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* @a2, align 4
+  ret i32 %0
+}
+
+; OPT1-LABEL: main2
+; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
+; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l
+; OPT1:      bl __tls_get_addr(a2@tlsgd)
+; OPT1-NEXT: nop
+
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll
index 46910a1357..2274edf8e1 100644
--- a/test/CodeGen/PowerPC/tls.ll
+++ b/test/CodeGen/PowerPC/tls.ll
@@ -1,5 +1,3 @@
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-freebsd10.0"
 ; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
 ; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
 
@@ -19,3 +17,22 @@ entry:
   store i32 42, i32* @a, align 4
   ret i32 0
 }
+
+; Test correct assembly code generation for thread-local storage
+; using the initial-exec model.
+
+@a2 = external thread_local global i32
+
+define signext i32 @main2() nounwind {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* @a2, align 4
+  ret i32 %0
+}
+
+; OPT1-LABEL: main2:
+; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha
+; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
+; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls
+