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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-22 17:28:28 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-11-22 17:28:28 +0000 |
| commit | b83bf521136801c1b9ea72dc9daae9428782cc75 (patch) | |
| tree | 549e24a130f57da2c6d8d0135b6fb507bd34269e /test | |
| parent | 4be5f33f6558438e6b104f9c74bf035bb77bdc10 (diff) | |
| download | llvm-b83bf521136801c1b9ea72dc9daae9428782cc75.tar.gz llvm-b83bf521136801c1b9ea72dc9daae9428782cc75.tar.bz2 llvm-b83bf521136801c1b9ea72dc9daae9428782cc75.tar.xz | |
[SystemZ] Fix TMHH and TMHL usage for z10 with -O0
I've no idea why I decided to handle TMxx differently from all the other
high/low logic operations, but it was a stupid thing to do. The high
registers aren't available as separate 32-bit registers on z10,
so subreg_h32 can't be used on a GR64 there.
I've normally been testing with z196 and with -O3 and so hadn't noticed
this until now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195473 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/SystemZ/int-cmp-47.ll | 1 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/int-cmp-49.ll | 49 |
2 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/int-cmp-47.ll b/test/CodeGen/SystemZ/int-cmp-47.ll index c770ccdbb9..9ebcbfe525 100644 --- a/test/CodeGen/SystemZ/int-cmp-47.ll +++ b/test/CodeGen/SystemZ/int-cmp-47.ll @@ -1,5 +1,6 @@ ; Test the use of TEST UNDER MASK for 64-bit operations. ; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s @g = global i32 0 diff --git a/test/CodeGen/SystemZ/int-cmp-49.ll b/test/CodeGen/SystemZ/int-cmp-49.ll new file mode 100644 index 0000000000..83f18a2a18 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-49.ll @@ -0,0 +1,49 @@ +; That that we don't try to use z196 instructions on z10 for TMHH and TMHL. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -O0 | FileCheck %s + +@g = global i32 0 + +; Check the lowest useful TMHL value. +define void @f1(i64 %a) { +; CHECK-LABEL: f1: +; CHECK-NOT: risblg +; CHECK-NOT: risbhg +; CHECK: tmhl {{%r[0-5]}}, 1 +; CHECK-NOT: risblg +; CHECK-NOT: risbhg +; CHECK: br %r14 +entry: + %and = and i64 %a, 4294967296 + %cmp = icmp eq i64 %and, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 1, i32 *@g + br label %exit + +exit: + ret void +} + +; Check the lowest useful TMHH value. +define void @f2(i64 %a) { +; CHECK-LABEL: f2: +; CHECK-NOT: risblg +; CHECK-NOT: risbhg +; CHECK: tmhh {{%r[0-5]}}, 1 +; CHECK-NOT: risblg +; CHECK-NOT: risbhg +; CHECK: br %r14 +entry: + %and = and i64 %a, 281474976710656 + %cmp = icmp ne i64 %and, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 1, i32 *@g + br label %exit + +exit: + ret void +} |