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| author | Andrew Trick <atrick@apple.com> | 2013-06-15 04:49:57 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-06-15 04:49:57 +0000 |
| commit | b86a0cdb674549d8493043331cecd9cbf53b80da (patch) | |
| tree | 8690d4a95ff7cf02b6f840632086b62aa1ed17fc /test | |
| parent | bacb24975d7a8a6ccff0e16057a581b3831c4c7d (diff) | |
| download | llvm-b86a0cdb674549d8493043331cecd9cbf53b80da.tar.gz llvm-b86a0cdb674549d8493043331cecd9cbf53b80da.tar.bz2 llvm-b86a0cdb674549d8493043331cecd9cbf53b80da.tar.xz | |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/misched-balance.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-matmul.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-matrix.ll | 19 |
3 files changed, 14 insertions, 12 deletions
diff --git a/test/CodeGen/X86/misched-balance.ll b/test/CodeGen/X86/misched-balance.ll index 2184d9e960..526b9d718d 100644 --- a/test/CodeGen/X86/misched-balance.ll +++ b/test/CodeGen/X86/misched-balance.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ -; RUN: -verify-machineinstrs | FileCheck %s +; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s +; RUN: true ; ; Verify that misched resource/latency balancy heuristics are sane. diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll index 15e8a0ad6f..7ad54bdc27 100644 --- a/test/CodeGen/X86/misched-matmul.ll +++ b/test/CodeGen/X86/misched-matmul.ll @@ -1,5 +1,6 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -stats 2>&1 | FileCheck %s +; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -stats 2>&1 | FileCheck %s +; RUN: true ; ; Verify that register pressure heuristics are working in MachineScheduler. ; diff --git a/test/CodeGen/X86/misched-matrix.ll b/test/CodeGen/X86/misched-matrix.ll index 4dc95c5e93..dee54d9c27 100644 --- a/test/CodeGen/X86/misched-matrix.ll +++ b/test/CodeGen/X86/misched-matrix.ll @@ -1,12 +1,13 @@ -; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ -; RUN: -misched-topdown -verify-machineinstrs \ -; RUN: | FileCheck %s -check-prefix=TOPDOWN -; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ -; RUN: -misched=ilpmin -verify-machineinstrs \ -; RUN: | FileCheck %s -check-prefix=ILPMIN -; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ -; RUN: -misched=ilpmax -verify-machineinstrs \ -; RUN: | FileCheck %s -check-prefix=ILPMAX +; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN-disabled: -misched-topdown -verify-machineinstrs \ +; RUN-disabled: | FileCheck %s -check-prefix=TOPDOWN +; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN-disabled: -misched=ilpmin -verify-machineinstrs \ +; RUN-disabled: | FileCheck %s -check-prefix=ILPMIN +; RUN-disabled: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN-disabled: -misched=ilpmax -verify-machineinstrs \ +; RUN-disabled: | FileCheck %s -check-prefix=ILPMAX +; RUN: true ; ; Verify that the MI scheduler minimizes register pressure for a ; uniform set of bottom-up subtrees (unrolled matrix multiply). |