[mips][msa] Add copy_{u,s}.d.

These instructions are only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 40 insertions, 0 deletions

diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll
index e268c2fd4e..0dd75fa3db 100644
--- a/test/CodeGen/Mips/msa/elm_copy.ll
+++ b/test/CodeGen/Mips/msa/elm_copy.ll
@@ -5,6 +5,10 @@
 ; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
 ; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
+; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
+; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
+; RUN:   FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64
 
 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
 @llvm_mips_copy_s_b_RES  = global i32 0, align 16
@@ -21,9 +25,11 @@ declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_s_b_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_ARG1)
 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_s_b_test
 ;
@@ -42,9 +48,11 @@ declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_s_h_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_ARG1)
 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_s_h_test
 ;
@@ -63,9 +71,11 @@ declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_s_w_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_ARG1)
 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_s_w_test
 ;
@@ -84,12 +94,17 @@ declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_s_d_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_ARG1)
 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
+; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
+; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_RES)
 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
+; MIPS64-DAG: sd [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_s_d_test
 ;
 @llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@@ -107,9 +122,11 @@ declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_u_b_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_ARG1)
 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_u_b_test
 ;
@@ -128,9 +145,11 @@ declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_u_h_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_ARG1)
 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_u_h_test
 ;
@@ -149,9 +168,11 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_u_w_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1)
 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES)
 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_u_w_test
 ;
@@ -170,11 +191,16 @@ declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind
 
 ; MIPS-ANY: llvm_mips_copy_u_d_test:
 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1)
+; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_ARG1)
 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
+; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
+; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1]
 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)
+; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES)
 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
+; MIPS64-DAG: sd [[RD]], 0([[RES]])
 ; MIPS-ANY: .size llvm_mips_copy_u_d_test
 ;
diff --git a/test/MC/Mips/msa/test_elm_msa64.s b/test/MC/Mips/msa/test_elm_msa64.s
new file mode 100644
index 0000000000..15bfcca247
--- /dev/null
+++ b/test/MC/Mips/msa/test_elm_msa64.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
+#
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \
+# RUN:   llvm-objdump -d -arch=mips64 -mattr=+msa - | \
+# RUN:     FileCheck %s -check-prefix=CHECKOBJDUMP
+#
+# CHECK:        copy_s.d        $19, $w31[0]             # encoding: [0x78,0xb8,0xfc,0xd9]
+# CHECK:        copy_u.d        $18, $w29[1]             # encoding: [0x78,0xf9,0xec,0x99]
+
+# CHECKOBJDUMP:        copy_s.d        $19, $w31[0]
+# CHECKOBJDUMP:        copy_u.d        $18, $w29[1]
+
+        copy_s.d        $19, $w31[0]
+        copy_u.d        $18, $w29[1]