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| author | Jim Grosbach <grosbach@apple.com> | 2011-09-14 20:03:46 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-09-14 20:03:46 +0000 |
| commit | bf841cf3360558d2939c9f1a244a7a7296f846df (patch) | |
| tree | ffb4229ed2993dfc0ec7d1fe70da77a2defbc085 /test | |
| parent | 97f50f3870fabfc7358543699fe608c59c61c2e6 (diff) | |
| download | llvm-bf841cf3360558d2939c9f1a244a7a7296f846df.tar.gz llvm-bf841cf3360558d2939c9f1a244a7a7296f846df.tar.bz2 llvm-bf841cf3360558d2939c9f1a244a7a7296f846df.tar.xz | |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 4 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 46 |
2 files changed, 48 insertions, 2 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 706c61c047..8691e15e16 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -838,7 +838,7 @@ Lforward: msr SPSR_fsxc, #5 msr cpsr_fsxc, #5 -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @@ -868,7 +868,7 @@ Lforward: msr SPSR_fsxc, r0 msr cpsr_fsxc, r0 -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1] @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index b51fb8c41b..bb399868b8 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -1063,6 +1063,52 @@ _func: @------------------------------------------------------------------------------ +@ MRS +@------------------------------------------------------------------------------ + mrs r8, apsr + mrs r8, cpsr + mrs r8, spsr + +@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88] +@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88] +@ CHECK: mrs r8, spsr @ encoding: [0xff,0xf3,0x00,0x88] + + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + msr apsr, r1 + msr apsr_g, r2 + msr apsr_nzcvq, r3 + msr APSR_nzcvq, r4 + msr apsr_nzcvqg, r5 + msr cpsr_fc, r6 + msr cpsr_c, r7 + msr cpsr_x, r8 + msr cpsr_fc, r9 + msr cpsr_all, r11 + msr cpsr_fsx, r12 + msr spsr_fc, r0 + msr SPSR_fsxc, r5 + msr cpsr_fsxc, r8 + +@ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88] +@ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84] +@ CHECK: msr APSR_nzcvq, r3 @ encoding: [0x83,0xf3,0x00,0x88] +@ CHECK: msr APSR_nzcvq, r4 @ encoding: [0x84,0xf3,0x00,0x88] +@ CHECK: msr APSR_nzcvqg, r5 @ encoding: [0x85,0xf3,0x00,0x8c] +@ CHECK: msr CPSR_fc, r6 @ encoding: [0x86,0xf3,0x00,0x89] +@ CHECK: msr CPSR_c, r7 @ encoding: [0x87,0xf3,0x00,0x81] +@ CHECK: msr CPSR_x, r8 @ encoding: [0x88,0xf3,0x00,0x82] +@ CHECK: msr CPSR_fc, r9 @ encoding: [0x89,0xf3,0x00,0x89] +@ CHECK: msr CPSR_fc, r11 @ encoding: [0x8b,0xf3,0x00,0x89] +@ CHECK: msr CPSR_fsx, r12 @ encoding: [0x8c,0xf3,0x00,0x8e] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] +@ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f] +@ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f] + + +@------------------------------------------------------------------------------ @ IT @------------------------------------------------------------------------------ @ Test encodings of a few full IT blocks, not just the IT instruction |