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authorOwen Anderson <resistor@mac.com>2010-09-21 18:41:19 +0000
committerOwen Anderson <resistor@mac.com>2010-09-21 18:41:19 +0000
commitc004eec71b49ae13ee4d9f859c61cdb9ed092b22 (patch)
tree23a74efbf817f08bb796242ade0c68d03bf68c17 /test
parent89bfef003ec71792d078d489566655006b89bc43 (diff)
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When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/add-of-carry.ll14
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll
new file mode 100644
index 0000000000..4c2257494d
--- /dev/null
+++ b/test/CodeGen/X86/add-of-carry.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; <rdar://problem/8449754>
+
+define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
+entry:
+; CHECK: sbbl %ecx, %ecx
+; CHECK-NOT: addl
+; CHECK: subl %ecx, %eax
+ %add4 = add i32 %x, %sum
+ %cmp = icmp ult i32 %add4, %x
+ %inc = zext i1 %cmp to i32
+ %z.0 = add i32 %add4, %inc
+ ret i32 %z.0
+}