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author | Tim Northover <tnorthover@apple.com> | 2013-08-27 10:31:36 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2013-08-27 10:31:36 +0000 |
commit | c59efb626a7a11ec661981e96ba09bba0497b731 (patch) | |
tree | beb23c6eee41bb68d9974199d8ce1c4933ee8361 /test | |
parent | 845ad06efb3b806726427f637911e69db31f4221 (diff) | |
download | llvm-c59efb626a7a11ec661981e96ba09bba0497b731.tar.gz llvm-c59efb626a7a11ec661981e96ba09bba0497b731.tar.bz2 llvm-c59efb626a7a11ec661981e96ba09bba0497b731.tar.xz |
ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/ARM/vadd.ll | 27 | ||||
-rw-r--r-- | test/CodeGen/ARM/vsub.ll | 27 |
2 files changed, 54 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll index a1ad37b5f8..c2c16aa132 100644 --- a/test/CodeGen/ARM/vadd.ll +++ b/test/CodeGen/ARM/vadd.ll @@ -152,6 +152,33 @@ declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind rea declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone +define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK-LABEL: vaddhni16_natural: +; CHECK: vaddhn.i16 + %sum = add <8 x i16> %A, %B + %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %trunc = trunc <8 x i16> %shift to <8 x i8> + ret <8 x i8> %trunc +} + +define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK-LABEL: vaddhni32_natural: +; CHECK: vaddhn.i32 + %sum = add <4 x i32> %A, %B + %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> + %trunc = trunc <4 x i32> %shift to <4 x i16> + ret <4 x i16> %trunc +} + +define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK-LABEL: vaddhni64_natural: +; CHECK: vaddhn.i64 + %sum = add <2 x i64> %A, %B + %shift = lshr <2 x i64> %sum, <i64 32, i64 32> + %trunc = trunc <2 x i64> %shift to <2 x i32> + ret <2 x i32> %trunc +} + define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddls8: ;CHECK: vaddl.s8 diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll index 89c3095ab2..8ed8d42459 100644 --- a/test/CodeGen/ARM/vsub.ll +++ b/test/CodeGen/ARM/vsub.ll @@ -121,6 +121,33 @@ declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind read declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone +define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK-LABEL: vsubhni16_natural: +; CHECK: vsubhn.i16 + %sum = sub <8 x i16> %A, %B + %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %trunc = trunc <8 x i16> %shift to <8 x i8> + ret <8 x i8> %trunc +} + +define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK-LABEL: vsubhni32_natural: +; CHECK: vsubhn.i32 + %sum = sub <4 x i32> %A, %B + %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> + %trunc = trunc <4 x i32> %shift to <4 x i16> + ret <4 x i16> %trunc +} + +define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK-LABEL: vsubhni64_natural: +; CHECK: vsubhn.i64 + %sum = sub <2 x i64> %A, %B + %shift = lshr <2 x i64> %sum, <i64 32, i64 32> + %trunc = trunc <2 x i64> %shift to <2 x i32> + ret <2 x i32> %trunc +} + define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrsubhni16: ;CHECK: vrsubhn.i16 |