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| author | Richard Osborne <richard@xmos.com> | 2013-04-04 19:57:46 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-04-04 19:57:46 +0000 |
| commit | c6ff29713d69b4a41c225cbde9c82e4a350dbfac (patch) | |
| tree | dc8d9d41936f30b018520c2c7e125b99d76b02a7 /test | |
| parent | 8256a98847ea90fae11ee95a0a3089e60f623b84 (diff) | |
| download | llvm-c6ff29713d69b4a41c225cbde9c82e4a350dbfac.tar.gz llvm-c6ff29713d69b4a41c225cbde9c82e4a350dbfac.tar.bz2 llvm-c6ff29713d69b4a41c225cbde9c82e4a350dbfac.tar.xz | |
[XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/XCore/xcore.txt | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 882d73a0e2..930bd0338d 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -456,36 +456,72 @@ # CHECK: ldaw r1, dp[456] 0x07 0xf0 0x48 0x60 +# CHECK: ldaw cp, dp[5] +0x05 0x63 + +# CHECK: ldaw sp, dp[9929] +0x9b 0xf0 0x89 0x63 + # CHECK: ldaw r3, sp[2] 0xc2 0x64 # CHECK: ldaw r8, sp[65535] 0xff 0xf3 0x3f 0x66 +# CHECK: ldaw sp, sp[41] +0xa9 0x67 + +# CHECK: ldaw sp, sp[13121] +0xcd 0xf0 0x81 0x67 + # CHECK: ldc r3, 30 0xde 0x68 # CHECK: ldc r11, 1000 0x0f 0xf0 0xe8 0x6a +# CHECK: ldc sp, 0 +0x80 0x6b + +# CHECK: ldc lr, 81 +0x01 0xf0 0xd1 0x6b + # CHECK: ldw r0, cp[4] 0x04 0x6c # CHECK: ldw r1, cp[32345] 0xf9 0xf1 0x59 0x6c +# CHECK: ldw cp, cp[8] +0x08 0x6f + +# CHECK: ldw sp, cp[10222] +0x9f 0xf0 0xae 0x6f + # CHECK: ldw r10, dp[16] 0x90 0x5a # CHECK: ldw r10, dp[76] 0x01 0xf0 0x8c 0x5a +# CHECK: ldw lr, dp[8] +0xc8 0x5b + +# CHECK: ldw dp, dp[33221] +0x07 0xf2 0x45 0x5b + # CHECK: ldw r8, sp[51] 0x33 0x5e # CHECK: ldw r8, sp[1225] 0x13 0xf0 0x09 0x5e +# CHECK: ldw cp, sp[31] +0x1f 0x5f + +# CHECK: ldw sp, sp[1000] +0x0f 0xf0 0xa8 0x5f + # CHECK: setc res[r5], 36 0x64 0xe9 @@ -498,12 +534,24 @@ # CHECK: stw r9, dp[654] 0x0a 0xf0 0x4e 0x52 +# CHECK: stw lr, dp[23] +0xd7 0x53 + +# CHECK: stw sp, dp[44442] +0xb6 0xf2 0x9a 0x53 + # CHECK: stw r1, sp[32] 0x60 0x54 # CHECK: stw r0, sp[8761] 0x88 0xf0 0x39 0x54 +# CHECK: stw cp, sp[63] +0x3f 0x57 + +# CHECK: stw lr, sp[4391] +0x44 0xf0 0xe7 0x57 + # u6 / lu6 instructions # CHECK: bu -20 |