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| author | Richard Osborne <richard@xmos.com> | 2013-01-20 18:37:49 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-20 18:37:49 +0000 |
| commit | c78ec6b6bc05572aed6af1eee4349d76a68ded18 (patch) | |
| tree | 5f86c1d07deee961a23ff87593636a8fd6e1d264 /test | |
| parent | a68c64fbb2f1bee7f9313f3ee19c35677563f974 (diff) | |
| download | llvm-c78ec6b6bc05572aed6af1eee4349d76a68ded18.tar.gz llvm-c78ec6b6bc05572aed6af1eee4349d76a68ded18.tar.bz2 llvm-c78ec6b6bc05572aed6af1eee4349d76a68ded18.tar.xz | |
Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/XCore/xcore.txt | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 5b7b375384..c86350e80a 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -257,3 +257,47 @@ # CHECK: sub r2, r4, 11 0x63 0x9d + +# l3r instructions + +# CHECK: ashr r5, r1, r11 +0xd7 0xfc 0xec 0x17 + +# CHECK: crc32 r5, r6, r1 +0x19 0xf9 0xec 0xaf + +# CHECK: divu r9, r1, r3 +0x97 0xf8 0xec 0x4f + +# CHECK: divs r6, r7, r2 +0x2e 0xf9 0xec 0x47 + +# CHECK: lda16 r11, r2[r1] +0xb9 0xf8 0xec 0x2f + +# CHECK: lda16 r9, r3[-r11] +0x1f 0xfd 0xec 0x37 + +# CHECK: ldaw r9, r1[r2] +0x96 0xf8 0xec 0x1f + +# CHECK: ldaw r8, r7[r11] +0xcf 0xfd 0xec 0x1f + +# CHECK: mul r0, r4, r2 +0xc2 0xf8 0xec 0x3f + +# CHECK: remu r1, r2, r3 +0x1b 0xf8 0xec 0xcf + +# CHECK: rems r11, r10, r9 +0xb9 0xfe 0xec 0xc7 + +# CHECK: st16 r5, r3[r8] +0xdc 0xfc 0xec 0x87 + +# CHECK: stw r7, r10[r1] +0xf9 0xf9 0xec 0x07 + +# CHECK: xor r4, r3, r9 +0xcd 0xfc 0xec 0x0f |