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author | Adam Nemet <anemet@apple.com> | 2014-05-20 17:20:34 +0000 |
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committer | Adam Nemet <anemet@apple.com> | 2014-05-20 17:20:34 +0000 |
commit | c9b12d06ef1ee950ed2125f6a810854e79e18929 (patch) | |
tree | b1c4fb7613453c06b7b261c4773c7de71398d2d1 /test | |
parent | 68c7a1cb98399c770af6dc103bec45b1b7ca3c29 (diff) | |
download | llvm-c9b12d06ef1ee950ed2125f6a810854e79e18929.tar.gz llvm-c9b12d06ef1ee950ed2125f6a810854e79e18929.tar.bz2 llvm-c9b12d06ef1ee950ed2125f6a810854e79e18929.tar.xz |
[PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate
The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64
backend. We matched an immediate offset with STWX8 even though it only
supports register offset.
The culprit is the complex-pattern predicate, SelectAddrIdx, which decides
that if the offset is not ISD::Constant it must be a register.
Many thanks to Bill Schmidt for testing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209219 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/PowerPC/indexed-load.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/indexed-load.ll b/test/CodeGen/PowerPC/indexed-load.ll new file mode 100644 index 0000000000..59fc058c94 --- /dev/null +++ b/test/CodeGen/PowerPC/indexed-load.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s | FileCheck %s + +; The SplitIndexingFromLoad tranformation exposed an isel backend bug. This +; testcase used to generate stwx 4, 3, 64. stwx does not have an +; immediate-offset format (note the 64) and it should not be matched. + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%class.test = type { [64 x i8], [5 x i8] } + +; CHECK-LABEL: f: +; CHECK-NOT: stwx {{[0-9]+}}, {{[0-9]+}}, 64 +define void @f(%class.test* %this) { +entry: + %Subminor.i.i = getelementptr inbounds %class.test* %this, i64 0, i32 1 + %0 = bitcast [5 x i8]* %Subminor.i.i to i40* + %bf.load2.i.i = load i40* %0, align 4 + %bf.clear7.i.i = and i40 %bf.load2.i.i, -8589934592 + store i40 %bf.clear7.i.i, i40* %0, align 4 + ret void +} |