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author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-21 23:17:56 +0000 |
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committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-21 23:17:56 +0000 |
commit | cba7ac7bda58e03d452f7e8ad73978744c101727 (patch) | |
tree | f644098b3ff2f30cd9a4efb71bad44a22ceef99a /test | |
parent | 159ccc8f51f7cb090058cfd0dcb64453f5681606 (diff) | |
download | llvm-cba7ac7bda58e03d452f7e8ad73978744c101727.tar.gz llvm-cba7ac7bda58e03d452f7e8ad73978744c101727.tar.bz2 llvm-cba7ac7bda58e03d452f7e8ad73978744c101727.tar.xz |
MC: correct IMAGE_REL_ARM_MOV32T relocation emission
This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we
were avoiding the high portion of the relocation too early. If there was a
section-relative relocation with an offset greater than 16-bits (65535), you
would end up truncating the high order bits of the offset. Allow the current
relocation representation to flow through out the MC layer to the object writer.
Use the new ability to restrict recorded relocations to avoid emitting the
relocation into the final object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/MC/ARM/Windows/mov32t-range.s | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/test/MC/ARM/Windows/mov32t-range.s b/test/MC/ARM/Windows/mov32t-range.s new file mode 100644 index 0000000000..fef8ff2aca --- /dev/null +++ b/test/MC/ARM/Windows/mov32t-range.s @@ -0,0 +1,37 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-RELOCATIONS %s + +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-objdump -d - | FileCheck -check-prefix CHECK-ENCODING %s + + .syntax unified + .thumb + .text + + .def truncation + .scl 3 + .type 32 + .endef + .align 2 + .thumb_func +truncation: + movw r0, :lower16:.Lerange + movt r0, :upper16:.Lerange + bx lr + + .section .rdata,"rd" +.Lbuffer: + .zero 65536 +.Lerange: + .asciz "-erange" + +@ CHECK-RELOCATIONS: Relocations [ +@ CHECK-RELOCATIONS: .text { +@ CHECK-RELOCATIONS: 0x0 IMAGE_REL_ARM_MOV32T .rdata +@ CHECK-RELOCATIONS-NOT: 0x4 IMAGE_REL_ARM_MOV32T .rdata +@ CHECK-RELOCATIONS: } +@ CHECK-RELOCATIONS: ] + +@ CHECK-ENCODING: 0: 40 f2 00 00 +@ CHECK-ENCODING-NEXT: 4: c0 f2 01 00 + |