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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-10-26 21:29:15 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-10-26 21:29:15 +0000
commitcd275f5687799e63956beabe35fc1718dc022f70 (patch)
treedf35df442b7a86b72ed82b088f60b36fb3a819f9 /test
parent6db893660ff92d4433350b5c084d123a50f4f122 (diff)
downloadllvm-cd275f5687799e63956beabe35fc1718dc022f70.tar.gz
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Add GPRPair Register class to ARM.
Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166816 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Thumb2/thumb2-uxtb.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 35914b1679..2074f98cb6 100644
--- a/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -128,9 +128,9 @@ define i32 @test10(i32 %p0) {
; ARMv7M: test10
; ARMv7M: mov.w r1, #16253176
-; ARMv7M: mov.w r2, #458759
; ARMv7M: and.w r0, r1, r0, lsr #7
-; ARMv7M: and.w r1, r2, r0, lsr #5
+; ARMv7M: mov.w r1, #458759
+; ARMv7M: and.w r1, r1, r0, lsr #5
; ARMv7M: orrs r0, r1
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]