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| author | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:20 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:20 +0000 |
| commit | d3293b49f9c7af741d2edd3062499fb50db0e89b (patch) | |
| tree | 06276066dbbab9472afd55701acbec7b7dade5ca /test | |
| parent | 4109bd8829c2736016a2eb9777ea0b52ba2f7d5c (diff) | |
| download | llvm-d3293b49f9c7af741d2edd3062499fb50db0e89b.tar.gz llvm-d3293b49f9c7af741d2edd3062499fb50db0e89b.tar.bz2 llvm-d3293b49f9c7af741d2edd3062499fb50db0e89b.tar.xz | |
R600: Improve texture handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.tex.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.tex.ll b/test/CodeGen/R600/llvm.AMDGPU.tex.ll index 81fd43d469..4ea82bb4c6 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.tex.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.tex.ll @@ -1,21 +1,21 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 1 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 2 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 3 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 4 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 5 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 6 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 7 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 8 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 9 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 10 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 11 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 12 -;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 13 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 14 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 15 -;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 16 +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %addr = load <4 x float> addrspace(1)* %in |