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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-01-24 23:28:42 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-01-24 23:28:42 +0000
commitd36f5af224594719a10d8b190daf4b56cdb7377f (patch)
tree38419ea63d70da10be2fd74ca7ab8c4a13ebe2e6 /test
parent1ce6a36610f06a1fb4047ddde1e9bc2f071c0bfb (diff)
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Set correct <def,undef> flags when lowering REG_SEQUENCE.
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll2
-rw-r--r--test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll43
2 files changed, 44 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
index b9d5600d2a..1aee5088ee 100644
--- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
+++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
@@ -12,7 +12,7 @@ target triple = "thumbv7-apple-darwin10"
; CHECK: vld1.64 {d16, d17}, [r{{.}}]
; CHECK-NOT: vld1.64 {d16, d17}
-; CHECK: vmov.f64 d19, d16
+; CHECK: vmov.f64
define i32 @test(i8* %arg) nounwind {
entry:
diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
new file mode 100644
index 0000000000..faf65b60be
--- /dev/null
+++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
+; PR11841
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
+target triple = "armv7-none-linux-eabi"
+
+; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
+define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
+bb:
+ %tmp = load <2 x float>* undef, align 8, !tbaa !0
+ %tmp2 = extractelement <2 x float> %tmp, i32 0
+ %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
+ %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
+ %tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2
+ %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
+ %tmp7 = extractelement <2 x float> %tmp, i32 1
+ %tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1
+ %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2
+ %tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3
+ %tmp11 = bitcast <4 x float> %tmp6 to <2 x i64>
+ %tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer
+ %tmp13 = bitcast <1 x i64> %tmp12 to <2 x float>
+ %tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer
+ %tmp15 = bitcast <4 x float> %tmp14 to <2 x i64>
+ %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
+ %tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
+ %tmp18 = extractelement <2 x float> %tmp17, i32 0
+ tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
+ %tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
+ %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
+ %tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
+ %tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
+ %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
+ %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
+ %tmp26 = extractelement <2 x float> %tmp25, i32 0
+ tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
+ ret void
+}
+
+declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
+
+!0 = metadata !{metadata !"omnipotent char", metadata !1}
+!1 = metadata !{metadata !"Simple C/C++ TBAA", null}