AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands

These can have different relocations in ELF. In particular both:

    b.eq global
    ldr x0, global

are valid, giving different relocations. The only possible way to distinguish
them is via a different fixup, so the operands had to be separated throughout
the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 20 insertions, 17 deletions

diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s
index d4c3a4eb50..55ba5f8b74 100644
--- a/test/MC/AArch64/elf-reloc-ldrlit.s
+++ b/test/MC/AArch64/elf-reloc-ldrlit.s
@@ -1,6 +1,9 @@
 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
 // RUN:   llvm-readobj -r | FileCheck -check-prefix=OBJ %s
 
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \
+// RUN:   llvm-readobj -r | FileCheck -check-prefix=OBJ %s
+
         ldr x0, some_label
         ldr w3, some_label
         ldrsw x9, some_label
diff --git a/test/MC/ARM64/branch-encoding.s b/test/MC/ARM64/branch-encoding.s
index 4574047f49..8f8751c2cc 100644
--- a/test/MC/ARM64/branch-encoding.s
+++ b/test/MC/ARM64/branch-encoding.s
@@ -31,49 +31,49 @@ foo:
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch26
   b.eq  L1
 ; CHECK: b.eq L1   ; encoding: [0bAAA00000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.ne  L1
 ; CHECK: b.ne L1   ; encoding: [0bAAA00001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cs  L1
 ; CHECK: b.cs L1   ; encoding: [0bAAA00010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cc  L1
 ; CHECK: b.cc L1   ; encoding: [0bAAA00011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.mi  L1
 ; CHECK: b.mi L1   ; encoding: [0bAAA00100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.pl  L1
 ; CHECK: b.pl L1   ; encoding: [0bAAA00101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.vs  L1
 ; CHECK: b.vs L1   ; encoding: [0bAAA00110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.vc  L1
 ; CHECK: b.vc L1   ; encoding: [0bAAA00111,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.hi  L1
 ; CHECK: b.hi L1   ; encoding: [0bAAA01000,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.ls  L1
 ; CHECK: b.ls L1   ; encoding: [0bAAA01001,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.ge  L1
 ; CHECK: b.ge L1   ; encoding: [0bAAA01010,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.lt  L1
 ; CHECK: b.lt L1   ; encoding: [0bAAA01011,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.gt  L1
 ; CHECK: b.gt L1   ; encoding: [0bAAA01100,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.le  L1
 ; CHECK: b.le L1   ; encoding: [0bAAA01101,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.al  L1
 ; CHECK: b.al L1      ; encoding: [0bAAA01110,A,A,0x54]
-; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
 L1:
   b #28
 ; CHECK: b #28
diff --git a/test/MC/ARM64/diags.s b/test/MC/ARM64/diags.s
index 424d9547fe..95b00a5b29 100644
--- a/test/MC/ARM64/diags.s
+++ b/test/MC/ARM64/diags.s
@@ -8,7 +8,7 @@ foo:
   ldr x3, (foo + 4)
   ldr x3, [foo + 4]
 ; CHECK:  ldr x3, foo+4               ; encoding: [0bAAA00011,A,A,0x58]
-; CHECK:                              ;   fixup A - offset: 0, value: foo+4, kind: fixup_arm64_pcrel_imm19
+; CHECK:                              ;   fixup A - offset: 0, value: foo+4, kind: fixup_arm64_ldr_pcrel_imm19
 ; CHECK-ERRORS: error: register expected
 
 ; The last argument should be flagged as an error.  rdar://9576009
diff --git a/test/MC/ARM64/tls-relocs.s b/test/MC/ARM64/tls-relocs.s
index acb30d9ef3..28c8ad9ef2 100644
--- a/test/MC/ARM64/tls-relocs.s
+++ b/test/MC/ARM64/tls-relocs.s
@@ -29,7 +29,7 @@
 // CHECK: ldr     x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
 // CHECK: ldr     x9, :gottprel:var       // encoding: [0bAAA01001,A,A,0x58]
-// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_imm19
+// CHECK-NEXT:                                 //   fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_ldr_pcrel_imm19
 
 // CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
 // CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]