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| author | Filipe Cabecinhas <me@filcab.net> | 2014-05-30 23:03:11 +0000 |
|---|---|---|
| committer | Filipe Cabecinhas <me@filcab.net> | 2014-05-30 23:03:11 +0000 |
| commit | d99cefbad17a3680601914ff73a28d3214f91c70 (patch) | |
| tree | 02b1d477b927c6a726d5915173371a3fed3736f5 /test | |
| parent | 96241f26fcbf6bc40a4ce1ea6c3c7ef8af22b7a9 (diff) | |
| download | llvm-d99cefbad17a3680601914ff73a28d3214f91c70.tar.gz llvm-d99cefbad17a3680601914ff73a28d3214f91c70.tar.bz2 llvm-d99cefbad17a3680601914ff73a28d3214f91c70.tar.xz | |
Convert a vselect into a concat_vector if possible
Summary:
If both vector args to vselect are concat_vectors and the condition is
constant and picks half a vector from each argument, convert the vselect
into a concat_vectors.
Added a test.
The ConvertSelectToConcatVector is assuming it doesn't get vselects with
arguments of, for example, <undef, undef, true, true>. Those get taken
care of in the checks above its call.
Reviewers: nadav, delena, grosbach, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D3916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209929 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Generic/select.ll | 1 | ||||
| -rw-r--r-- | test/CodeGen/X86/vselect.ll | 14 |
2 files changed, 14 insertions, 1 deletions
diff --git a/test/CodeGen/Generic/select.ll b/test/CodeGen/Generic/select.ll index 77636eb6e6..c4841b79ac 100644 --- a/test/CodeGen/Generic/select.ll +++ b/test/CodeGen/Generic/select.ll @@ -192,4 +192,3 @@ define <1 x i32> @checkScalariseVSELECT(<1 x i32> %a, <1 x i32> %b) { %s = select <1 x i1> %cond, <1 x i32> %a, <1 x i32> %b ret <1 x i32> %s } - diff --git a/test/CodeGen/X86/vselect.ll b/test/CodeGen/X86/vselect.ll index 0cf03fc5d6..42cf06a4a0 100644 --- a/test/CodeGen/X86/vselect.ll +++ b/test/CodeGen/X86/vselect.ll @@ -262,3 +262,17 @@ define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) { ; CHECK: movsd ; CHECK: ret +define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) { +; CHECK-LABEL: select_of_shuffles_0 +; CHECK-DAG: movlhps %xmm2, [[REGA:%xmm[0-9]+]] +; CHECK-DAG: movlhps %xmm3, [[REGB:%xmm[0-9]+]] +; CHECK: subps [[REGB]], [[REGA]] + %1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + %2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> + %3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1 + %4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + %5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> + %6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4 + %7 = fsub <4 x float> %3, %6 + ret <4 x float> %7 +} |