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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-01 20:31:44 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-01 20:31:44 +0000 |
| commit | db8e0bbedb46c9f781f8a32728b1019f34089ed8 (patch) | |
| tree | 96b227e24c3487d12b99961e0a559adead2def4e /test | |
| parent | ae99e41ff45b0fdd432975f8e7763167b57bcaf5 (diff) | |
| download | llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.tar.gz llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.tar.bz2 llvm-db8e0bbedb46c9f781f8a32728b1019f34089ed8.tar.xz | |
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32_le.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32r2.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32r2_le.txt | 8 |
4 files changed, 16 insertions, 16 deletions
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 5c2d5ca476..ef8bf71bd3 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 $6, $fcc0 -0x44 0x46 0x08 0x00 +# CHECK: cfc1 $6, $7 +0x44 0x46 0x38 0x00 # CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 $6, $fcc0 -0x44 0xc6 0x08 0x00 +# CHECK: ctc1 $6, $7 +0x44 0xc6 0x38 0x00 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index f0553c68f8..a0885a4bfe 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 -# CHECK: cfc1 $6, $fcc0 -0x00 0x08 0x46 0x44 +# CHECK: cfc1 $6, $7 +0x00 0x38 0x46 0x44 # CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 $6, $fcc0 -0x00 0x08 0xc6 0x44 +# CHECK: ctc1 $6, $7 +0x00 0x38 0xc6 0x44 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index ac20e411c1..991eaa6cc9 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 $6, $fcc0 -0x44 0x46 0x08 0x00 +# CHECK: cfc1 $6, $7 +0x44 0x46 0x38 0x00 # CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 $6, $fcc0 -0x44 0xc6 0x08 0x00 +# CHECK: ctc1 $6, $7 +0x44 0xc6 0x38 0x00 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index a9131a35f8..10c293821c 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 -# CHECK: cfc1 $6, $fcc0 -0x00 0x08 0x46 0x44 +# CHECK: cfc1 $6, $7 +0x00 0x38 0x46 0x44 # CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 $6, $fcc0 -0x00 0x08 0xc6 0x44 +# CHECK: ctc1 $6, $7 +0x00 0x38 0xc6 0x44 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 |