diff options
| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-02-10 14:24:23 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-02-10 14:24:23 +0000 |
| commit | dbd5c285b8a878ef068b6fb05f1981cf4878f0db (patch) | |
| tree | e2e04bd0f1cbedcddfdb1e5e534095626a673006 /test | |
| parent | 299918ad4813ded5eb717c0c4898eb67205d880b (diff) | |
| download | llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.gz llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.bz2 llvm-dbd5c285b8a878ef068b6fb05f1981cf4878f0db.tar.xz | |
ARM: r12 is callee-saved for interrupt handlers
For A- and R-class processors, r12 is not normally callee-saved, but is for
interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/interrupt-attr.ll | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 10d5c00a85..a006bb62be 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -12,24 +12,24 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Also need special function return setting pc and CPSR simultaneously. ; CHECK-A-LABEL: irq_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: add r11, sp, #16 ; CHECK-A: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; CHECK-A: bl bar ; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 ; CHECK-A-THUMB-LABEL: irq_fn: -; CHECK-A-THUMB: push {r0, r1, r2, r3, r4, r7, lr} +; CHECK-A-THUMB: push.w {r0, r1, r2, r3, r4, r7, r12, lr} ; CHECK-A-THUMB: mov r4, sp ; CHECK-A-THUMB: add r7, sp, #20 ; CHECK-A-THUMB: bic r4, r4, #7 ; CHECK-A-THUMB: bl bar ; CHECK-A-THUMB: sub.w r4, r7, #20 ; CHECK-A-THUMB: mov sp, r4 -; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, lr} +; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, r12, lr} ; CHECK-A-THUMB: subs pc, lr, #4 ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to @@ -49,6 +49,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ret void } +; We don't push/pop r12, as it is banked for FIQ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { ; CHECK-A-LABEL: fiq_fn: ; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr} @@ -71,13 +72,13 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { ; CHECK-A-LABEL: swi_fn: -; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #44 ; CHECK-A: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] ; CHECK-A: sub sp, r11, #44 -; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 %val = load volatile [16 x i32]* @bigvar @@ -87,13 +88,13 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { ; CHECK-A-LABEL: undef_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: add r11, sp, #16 ; CHECK-A: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] ; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 call void @bar() @@ -102,13 +103,13 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { ; CHECK-A-LABEL: abort_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: add r11, sp, #16 ; CHECK-A: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] ; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 call void @bar() |