Track IR ordering of SelectionDAG nodes 3/4.

Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 14 insertions, 14 deletions

diff --git a/test/CodeGen/AArch64/sincos-expansion.ll b/test/CodeGen/AArch64/sincos-expansion.ll
index c7a392b78c..f1b7441118 100644
--- a/test/CodeGen/AArch64/sincos-expansion.ll
+++ b/test/CodeGen/AArch64/sincos-expansion.ll
@@ -3,8 +3,8 @@
 define float @test_sincos_f32(float %f) {
   %sin = call float @sinf(float %f) readnone
   %cos = call float @cosf(float %f) readnone
-; CHECK: bl cosf
 ; CHECK: bl sinf
+; CHECK: bl cosf
   %val = fadd float %sin, %cos
   ret float %val
 }
@@ -13,8 +13,8 @@ define double @test_sincos_f64(double %f) {
   %sin = call double @sin(double %f) readnone
   %cos = call double @cos(double %f) readnone
   %val = fadd double %sin, %cos
-; CHECK: bl cos
 ; CHECK: bl sin
+; CHECK: bl cos
   ret double %val
 }
 
@@ -22,8 +22,8 @@ define fp128 @test_sincos_f128(fp128 %f) {
   %sin = call fp128 @sinl(fp128 %f) readnone
   %cos = call fp128 @cosl(fp128 %f) readnone
   %val = fadd fp128 %sin, %cos
-; CHECK: bl cosl
 ; CHECK: bl sinl
+; CHECK: bl cosl
   ret fp128 %val
 }
 
diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll
index 216057a313..91de08a187 100644
--- a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll
+++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll
@@ -42,7 +42,7 @@ if.then:                                          ; preds = %land.lhs.true
 ; If-convert the return
 ; CHECK: it	ne
 ; Fold the CSR+return into a pop
-; CHECK: popne	{r4, r5, r7, pc}
+; CHECK: pop {r4, r5, r6, r7, pc}
 sw.bb18:
   %call20 = tail call i32 @bar(i32 %in2) nounwind
   switch i32 %call20, label %sw.default56 [
diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll
index 6bb9ea3a8c..da7007bd4a 100644
--- a/test/CodeGen/ARM/fast-isel-pic.ll
+++ b/test/CodeGen/ARM/fast-isel-pic.ll
@@ -15,7 +15,7 @@ entry:
 ; THUMB-ELF: LoadGV
 ; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],
 ; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],
-; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]]
+; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
 ; ARM: LoadGV
 ; ARM: ldr [[reg1:r[0-9]+]],
 ; ARM: add [[reg1]], pc, [[reg1]]
@@ -26,7 +26,7 @@ entry:
 ; ARMv7-ELF: LoadGV
 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
+; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]], r[[reg3]]]
   %tmp = load i32* @g
   ret i32 %tmp
 }
@@ -43,7 +43,7 @@ entry:
 ; THUMB-ELF: LoadIndirectSymbol
 ; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],
 ; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],
-; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]]
+; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
 ; ARM: LoadIndirectSymbol
 ; ARM: ldr [[reg4:r[0-9]+]],
 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
@@ -55,7 +55,7 @@ entry:
 ; ARMv7-ELF: LoadIndirectSymbol
 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
+; ARMv7-ELF: ldr r[[reg5]], [r[[reg5]], r[[reg6]]]
   %tmp = load i32* @i
   ret i32 %tmp
 }
diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll
index 333c4663eb..f800c5861d 100644
--- a/test/CodeGen/X86/sincos-opt.ll
+++ b/test/CodeGen/X86/sincos-opt.ll
@@ -19,8 +19,8 @@ entry:
 ; OSX_SINCOS: addss %xmm0, %xmm1
 
 ; OSX_NOOPT: test1
-; OSX_NOOPT: callq _cosf
 ; OSX_NOOPT: callq _sinf
+; OSX_NOOPT: callq _cosf
   %call = tail call float @sinf(float %x) nounwind readnone
   %call1 = tail call float @cosf(float %x) nounwind readnone
   %add = fadd float %call, %call1
@@ -39,8 +39,8 @@ entry:
 ; OSX_SINCOS: addsd %xmm1, %xmm0
 
 ; OSX_NOOPT: test2
-; OSX_NOOPT: callq _cos
 ; OSX_NOOPT: callq _sin
+; OSX_NOOPT: callq _cos
   %call = tail call double @sin(double %x) nounwind readnone
   %call1 = tail call double @cos(double %x) nounwind readnone
   %add = fadd double %call, %call1
diff --git a/test/CodeGen/X86/win32_sret.ll b/test/CodeGen/X86/win32_sret.ll
index 2bfe5fb100..a24963a3f3 100644
--- a/test/CodeGen/X86/win32_sret.ll
+++ b/test/CodeGen/X86/win32_sret.ll
@@ -115,8 +115,8 @@ entry:
 
 ; Load the address of the result and put it onto stack
 ; (through %ecx in the -O0 build).
-; WIN32:      leal {{[0-9]+}}(%esp), %eax
-; WIN32:      movl %eax, (%e{{[sc][px]}})
+; WIN32:      leal {{[0-9]+}}(%esp), %e{{[a-d]}}x
+; WIN32:      movl %e{{[a-d]}}x, (%e{{([a-d]x)|(sp)}})
 
 ; The this pointer goes to ECX.
 ; WIN32-NEXT: leal {{[0-9]+}}(%esp), %ecx
diff --git a/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll b/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
index cb23ad01a4..8053940df1 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
@@ -11,9 +11,9 @@ declare i1 @check() nounwind
 
 ; Check that LSR did something close to the behavior at the time of the bug.
 ; CHECK: @sqlite3DropTriggerPtr
-; CHECK: incq %rax
+; CHECK: incq %r{{[a-d]}}x
 ; CHECK: jne
-; CHECK: decq %rax
+; CHECK: decq %r{{[a-d]}}x
 ; CHECK: ret
 define i64 @sqlite3DropTriggerPtr() nounwind {
 bb: