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| author | Bob Wilson <bob.wilson@apple.com> | 2009-08-19 17:03:43 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-08-19 17:03:43 +0000 |
| commit | de95c1b88be44d4af916af8fba9d7940b7e98e32 (patch) | |
| tree | 26d10df107ad8809ef8778b5473ba884ccb59ccb /test | |
| parent | 12a8a447a4ca5b939f255ae92e7fef490344593a (diff) | |
| download | llvm-de95c1b88be44d4af916af8fba9d7940b7e98e32.tar.gz llvm-de95c1b88be44d4af916af8fba9d7940b7e98e32.tar.bz2 llvm-de95c1b88be44d4af916af8fba9d7940b7e98e32.tar.xz | |
Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/vext.ll | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll new file mode 100644 index 0000000000..a9d66467d8 --- /dev/null +++ b/test/CodeGen/ARM/vext.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s + +define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: test_vextd: +;CHECK: vext + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> + ret <8 x i8> %tmp3 +} + +define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: test_vextRd: +;CHECK: vext + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> + ret <8 x i8> %tmp3 +} + +define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: test_vextq: +;CHECK: vext + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> + ret <16 x i8> %tmp3 +} + +define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: test_vextRq: +;CHECK: vext + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> + ret <16 x i8> %tmp3 +} |