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authorBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-04-02 18:37:08 +0000
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>2013-04-02 18:37:08 +0000
commitdebf7d345aa297ebedf2d3b1db234feb44c71483 (patch)
tree7bd30cb38b9d63a8a18299c764a5735aad53cba0 /test
parent423d6744123e4886f9f79f6273fa345b9cce51a8 (diff)
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Fix PR15630: Replace faulty stdcx. with stwcx.
When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/PowerPC/pr15630.ll16
1 files changed, 16 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/pr15630.ll b/test/CodeGen/PowerPC/pr15630.ll
new file mode 100644
index 0000000000..c5ba8a4d4f
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr15630.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define weak_odr void @_D4core6atomic49__T11atomicStoreVE4core6atomic11MemoryOrder3ThThZ11atomicStoreFNaNbKOhhZv(i8* %val_arg, i8 zeroext %newval_arg) {
+entry:
+ %newval = alloca i8
+ %ordering = alloca i32, align 4
+ store i8 %newval_arg, i8* %newval
+ %tmp = load i8* %newval
+ store atomic volatile i8 %tmp, i8* %val_arg seq_cst, align 1
+ ret void
+}
+
+; CHECK: stwcx.