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authorDaniel Sanders <daniel.sanders@imgtec.com>2014-03-04 13:54:30 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2014-03-04 13:54:30 +0000
commite06bec47d646adb36c0bc552e8a0ed86d901d012 (patch)
tree428a163432fed19b509b9c298ddaa4691e418052 /test
parent80a59df0e7b0c00c579827727f01fb5038f08ef7 (diff)
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[mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.
Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/Mips/msa/basic_operations_float.ll18
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll
index a405e1b6de..c8cef44909 100644
--- a/test/CodeGen/Mips/msa/basic_operations_float.ll
+++ b/test/CodeGen/Mips/msa/basic_operations_float.ll
@@ -137,6 +137,24 @@ define float @extract_v4f32_elt0() nounwind {
; MIPS32: .size extract_v4f32_elt0
}
+define float @extract_v4f32_elt2() nounwind {
+ ; MIPS32: extract_v4f32_elt2:
+
+ %1 = load <4 x float>* @v4f32
+ ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+
+ %2 = fadd <4 x float> %1, %1
+ ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
+
+ %3 = extractelement <4 x float> %2, i32 2
+ ; Element 2 can be obtained by splatting it across the vector and extracting
+ ; $w0:sub_lo
+ ; MIPS32-DAG: splati.w $w0, [[R1]][2]
+
+ ret float %3
+ ; MIPS32: .size extract_v4f32_elt2
+}
+
define double @extract_v2f64() nounwind {
; MIPS32: extract_v2f64: