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| author | Chad Rosier <mcrosier@apple.com> | 2011-11-02 18:08:25 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-11-02 18:08:25 +0000 |
| commit | e07cd5e40ac06fabfb9d33ea7c79542f138f45ce (patch) | |
| tree | 0c5a59347cb4e87079b41bbd6ed1830161fb738c /test | |
| parent | 81550dc0a866e27a1efbc5de616fb366ebb547cd (diff) | |
| download | llvm-e07cd5e40ac06fabfb9d33ea7c79542f138f45ce.tar.gz llvm-e07cd5e40ac06fabfb9d33ea7c79542f138f45ce.tar.bz2 llvm-e07cd5e40ac06fabfb9d33ea7c79542f138f45ce.tar.xz | |
Add support for comparing integer non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-icmp.ll | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-icmp.ll b/test/CodeGen/ARM/fast-isel-icmp.ll new file mode 100644 index 0000000000..deffe7bdb6 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-icmp.ll @@ -0,0 +1,47 @@ +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB + +define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { +entry: +; ARM: icmp_i16_unsigned +; ARM: uxth r0, r0 +; ARM: uxth r1, r1 +; ARM: cmp r0, r1 +; THUMB: icmp_i16_unsigned +; THUMB: uxth r0, r0 +; THUMB: uxth r1, r1 +; THUMB: cmp r0, r1 + %cmp = icmp ult i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { +entry: +; ARM: icmp_i8_signed +; ARM: sxtb r0, r0 +; ARM: sxtb r1, r1 +; ARM: cmp r0, r1 +; THUMB: icmp_i8_signed +; THUMB: sxtb r0, r0 +; THUMB: sxtb r1, r1 +; THUMB: cmp r0, r1 + %cmp = icmp sgt i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind { +entry: +; ARM: icmp_i1_unsigned +; ARM: and r0, r0, #1 +; ARM: and r1, r1, #1 +; ARM: cmp r0, r1 +; THUMB: icmp_i1_unsigned +; THUMB: and r0, r0, #1 +; THUMB: and r1, r1, #1 +; THUMB: cmp r0, r1 + %cmp = icmp ult i1 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} |