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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 13:04:21 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 13:04:21 +0000 |
| commit | e8eafdb67685d4f5d52ab0dce2339c37e39cdc44 (patch) | |
| tree | fb1d2c07976e88b2437f09fa5b0b479b57431f42 /test | |
| parent | b0922655166aeef6c54c7b4d31d1ccaecf492e2e (diff) | |
| download | llvm-e8eafdb67685d4f5d52ab0dce2339c37e39cdc44.tar.gz llvm-e8eafdb67685d4f5d52ab0dce2339c37e39cdc44.tar.bz2 llvm-e8eafdb67685d4f5d52ab0dce2339c37e39cdc44.tar.xz | |
[mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/Mips/msa/elm_copy.ll | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll index c32dd8b591..4bf041e29e 100644 --- a/test/CodeGen/Mips/msa/elm_copy.ll +++ b/test/CodeGen/Mips/msa/elm_copy.ll @@ -60,6 +60,27 @@ declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind ; CHECK: sw ; CHECK: .size llvm_mips_copy_s_w_test ; +@llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 +@llvm_mips_copy_s_d_RES = global i64 0, align 16 + +define void @llvm_mips_copy_s_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_copy_s_d_ARG1 + %1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1) + store i64 %1, i64* @llvm_mips_copy_s_d_RES + ret void +} + +declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind + +; CHECK: llvm_mips_copy_s_d_test: +; CHECK: ld.w +; CHECK: copy_s.w +; CHECK: copy_s.w +; CHECK: sw +; CHECK: sw +; CHECK: .size llvm_mips_copy_s_d_test +; @llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_copy_u_b_RES = global i32 0, align 16 @@ -117,3 +138,24 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind ; CHECK: sw ; CHECK: .size llvm_mips_copy_u_w_test ; +@llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 +@llvm_mips_copy_u_d_RES = global i64 0, align 16 + +define void @llvm_mips_copy_u_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_copy_u_d_ARG1 + %1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1) + store i64 %1, i64* @llvm_mips_copy_u_d_RES + ret void +} + +declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind + +; CHECK: llvm_mips_copy_u_d_test: +; CHECK: ld.w +; CHECK: copy_s.w +; CHECK: copy_s.w +; CHECK: sw +; CHECK: sw +; CHECK: .size llvm_mips_copy_u_d_test +; |