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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:22 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:22 +0000 |
| commit | f586a260ca729c933cb15c6e68cabe95163a6dcb (patch) | |
| tree | 37baaed41e14f40cc2608c7bc0bae18bd9753163 /test | |
| parent | b02d95cb66157aa49bf5e50a8778c182a7b8604e (diff) | |
| download | llvm-f586a260ca729c933cb15c6e68cabe95163a6dcb.tar.gz llvm-f586a260ca729c933cb15c6e68cabe95163a6dcb.tar.bz2 llvm-f586a260ca729c933cb15c6e68cabe95163a6dcb.tar.xz | |
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/R600/sint_to_fp64.ll | 8 | ||||
| -rw-r--r-- | test/CodeGen/R600/uint_to_fp.f64.ll | 8 |
2 files changed, 10 insertions, 6 deletions
diff --git a/test/CodeGen/R600/sint_to_fp64.ll b/test/CodeGen/R600/sint_to_fp64.ll index f8e5acfd5e..12b8cf57cf 100644 --- a/test/CodeGen/R600/sint_to_fp64.ll +++ b/test/CodeGen/R600/sint_to_fp64.ll @@ -10,9 +10,11 @@ define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) { ; SI-LABEL: @sint_to_fp_i1_f64: ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], -; SI-NEXT: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: V_CVT_F64_I32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], +; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs, +; we should be able to fold the SGPRs into the V_CNDMASK instructions. +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: BUFFER_STORE_DWORDX2 ; SI: S_ENDPGM define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 diff --git a/test/CodeGen/R600/uint_to_fp.f64.ll b/test/CodeGen/R600/uint_to_fp.f64.ll index b5137a0768..9a41796a06 100644 --- a/test/CodeGen/R600/uint_to_fp.f64.ll +++ b/test/CodeGen/R600/uint_to_fp.f64.ll @@ -11,9 +11,11 @@ define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) { ; SI-LABEL: @uint_to_fp_i1_f64: ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], -; SI-NEXT: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]+]], 0, 1, [[CMP]] -; SI-NEXT: V_CVT_F64_U32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], +; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs, +; we should be able to fold the SGPRs into the V_CNDMASK instructions. +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: BUFFER_STORE_DWORDX2 ; SI: S_ENDPGM define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 |