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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-18 22:32:43 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-18 22:32:43 +0000 |
| commit | fbf19ef1860e33b202ff73a269b8b0bf9157460e (patch) | |
| tree | dd7fb999ae23ec2c77099e06d3758c85df5d5ad7 /test | |
| parent | e4824714026a528fe4cb08ad73e048066980eda6 (diff) | |
| download | llvm-fbf19ef1860e33b202ff73a269b8b0bf9157460e.tar.gz llvm-fbf19ef1860e33b202ff73a269b8b0bf9157460e.tar.bz2 llvm-fbf19ef1860e33b202ff73a269b8b0bf9157460e.tar.xz | |
Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142434 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/2011-10-19-LegelizeLoad.ll | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll new file mode 100644 index 0000000000..a7207537de --- /dev/null +++ b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i8:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%union.anon = type { <2 x i8> } + +@i = global <2 x i8> <i8 150, i8 100>, align 8 +@j = global <2 x i8> <i8 10, i8 13>, align 8 +@res = common global %union.anon zeroinitializer, align 8 + +; Make sure we load the constants i and j starting offset zero. +; Also make sure that we sign-extend it. +; Based on /gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c + +; CHECK: main +define i32 @main() nounwind uwtable { +entry: +; CHECK: movsbq j(%rip), % +; CHECK: movsbq i(%rip), % + %0 = load <2 x i8>* @i, align 8 + %1 = load <2 x i8>* @j, align 8 + %div = sdiv <2 x i8> %1, %0 + store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon* @res, i32 0, i32 0), align 8 + ret i32 0 +; CHECK: ret +} + |