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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 11:55:58 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 11:55:58 +0000 |
| commit | 14e97c4f51af68c71ebe0fba961aa49f1ac9c185 (patch) | |
| tree | 0f4a8e396b759d2281f06eb05f834a7be5758213 /tools/llvm-ar | |
| parent | 24ba4fa9e1c5a44edeca6833b8e4cbfe674e7622 (diff) | |
| download | llvm-14e97c4f51af68c71ebe0fba961aa49f1ac9c185.tar.gz llvm-14e97c4f51af68c71ebe0fba961aa49f1ac9c185.tar.bz2 llvm-14e97c4f51af68c71ebe0fba961aa49f1ac9c185.tar.xz | |
[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64
Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().
Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.
Depends on D3956
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'tools/llvm-ar')
0 files changed, 0 insertions, 0 deletions