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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-12 13:35:43 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-12 13:35:43 +0000 |
| commit | 58b6bfeb229acfe4ded95af6099024a3411ead74 (patch) | |
| tree | b16f42f46e842d24a2428b77f9866ae7f8b7d0fa /unittests/Transforms/Utils | |
| parent | fe6bd52bf2ac280ef2ab6ed0d95563d100cd68cd (diff) | |
| download | llvm-58b6bfeb229acfe4ded95af6099024a3411ead74.tar.gz llvm-58b6bfeb229acfe4ded95af6099024a3411ead74.tar.bz2 llvm-58b6bfeb229acfe4ded95af6099024a3411ead74.tar.xz | |
[mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower 32-bits of 64-bit FPR
Summary:
This is a white lie to workaround a widespread bug in the -mfp64
implementation.
The problem is that none of the 32-bit fpu ops mention the fact that they
clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be
scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1.
Fixing that requires a major overhaul of the FPU implementation which can't
be done right now due to time constraints.
The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given
TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'.
Also correct the comment added in r203464 to indicate that two
instructions were affected.
Reviewers: matheusalmeida, jacksprat
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203659 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'unittests/Transforms/Utils')
0 files changed, 0 insertions, 0 deletions